[llvm] 1ecdbf2 - [RISCV] Add SRAI to recursive part of isSignExtendedW. (#157164)

[via llvm-commits]

Author: Craig Topper
Date: 2025-09-05T13:02:11-07:00
New Revision: 1ecdbf2f2a728a2bb614501aa1a5adb0e18131b9

URL: https://github.com/llvm/llvm-project/commit/1ecdbf2f2a728a2bb614501aa1a5adb0e18131b9
DIFF: https://github.com/llvm/llvm-project/commit/1ecdbf2f2a728a2bb614501aa1a5adb0e18131b9.diff

LOG: [RISCV] Add SRAI to recursive part of isSignExtendedW. (#157164)

SRAI can only increase the number of sign bits. If the input has at
least 33 sign bits, the result will to.

I don't have a test case for this currently. It was just an observation
I made while thinking about the shifts and extracts.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 2168710e8bfa8..d4344416a0fef 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -529,9 +529,11 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
     case RISCV::ANDI:
     case RISCV::ORI:
     case RISCV::XORI:
+    case RISCV::SRAI:
       // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
       // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
       // Logical operations use a sign extended 12-bit immediate.
+      // Arithmetic shift right can only increase the number of sign bits.
       if (!AddRegToWorkList(MI->getOperand(1).getReg()))
         return false;