[llvm] [AVR] Refactor ADIW/SBIW/MOVW instruction descriptions (NFCI) (PR #156876)

[Sergei Barannikov via llvm-commits]

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@@ -91,6 +98,22 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeDREGSRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
+  assert(isUInt<4>(RegNo));
+  Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[RegNo]));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeIWREGSRegisterClass(MCInst &Inst, unsigned RegNo,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
+  assert(isUInt<2>(RegNo));
+  Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[12 + RegNo]));
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s-barannikov wrote:

Added a comment

https://github.com/llvm/llvm-project/pull/156876