[llvm] [RISCV] Move Xqci Select-likes to use riscv_selectcc (PR #153147)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 2 21:06:19 PDT 2025
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/153147
>From bf818014f0d56d68d5782920d92c9f4b231f1deb Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 8 Aug 2025 11:31:31 -0700
Subject: [PATCH 01/14] [RISCV] Use riscv_selectcc for Xqci
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 130 +++---
llvm/test/CodeGen/RISCV/select-cond.ll | 429 +++++++++++++-------
llvm/test/CodeGen/RISCV/xqcicli.ll | 24 +-
llvm/test/CodeGen/RISCV/xqcicm.ll | 67 ++-
5 files changed, 413 insertions(+), 240 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e63b9374ebe25..6961df8ab723a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -436,8 +436,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ABS, MVT::i32, Custom);
}
- if (!Subtarget.useCCMovInsn() && !Subtarget.hasVendorXTHeadCondMov() &&
- !Subtarget.hasVendorXqcicm() && !Subtarget.hasVendorXqcics())
+ if (!Subtarget.useCCMovInsn() && !Subtarget.hasVendorXTHeadCondMov())
setOperationAction(ISD::SELECT, XLenVT, Custom);
if (Subtarget.hasVendorXqcia() && !Subtarget.is64Bit()) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 2c64b0c220fba..59738a979c540 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1334,51 +1334,51 @@ class QCScaledStPat<PatFrag StoreOp, RVInst Inst>
(Inst GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
class QCIMVCCPat<CondCode Cond, QCIMVCC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond)), (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3)>;
class QCIMVCCIPat<CondCode Cond, QCIMVCCI Inst, DAGOperand InTyImm>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond)), (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, GPRNoX0:$rs3)>;
class QCISELECTCCIPat<CondCode Cond, QCISELECTCCI Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), simm5:$imm, Cond)), (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), simm5:$imm, Cond, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3)>;
class QCISELECTICCIPat<CondCode Cond, QCISELECTICCI Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), simm5:$imm, Cond)), (i32 GPRNoX0:$rs2), simm5:$simm2),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), simm5:$imm, Cond, (i32 GPRNoX0:$rs2), simm5:$simm2)),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCIPatInv<CondCode Cond, QCISELECTICCI Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), simm5:$imm, Cond)), simm5:$simm2, (i32 GPRNoX0:$rs2)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), simm5:$imm, Cond, simm5:$simm2, (i32 GPRNoX0:$rs2))),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCPat<CondCode Cond, QCISELECTICC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond)), (i32 GPRNoX0:$rs2), simm5:$simm2),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond, (i32 GPRNoX0:$rs2), simm5:$simm2)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCPatInv<CondCode Cond, QCISELECTICC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond)), simm5:$simm2, (i32 GPRNoX0:$rs2)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond, simm5:$simm2, (i32 GPRNoX0:$rs2))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTIICCPat<CondCode Cond, QCISELECTIICC Inst>
- : Pat<(select (i32 (setcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond)), simm5:$simm1, simm5:$simm2),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs1), Cond, simm5:$simm1, simm5:$simm2)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2)>;
class QCILICCPat<CondCode Cond, QCILICC Inst>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), (XLenVT GPRNoX0:$rs2), Cond)), simm5:$simm, (XLenVT GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond, simm5:$simm, (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm)>;
class QCILICCPatInv<CondCode Cond, QCILICC Inst>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), (XLenVT GPRNoX0:$rs2), Cond)), (XLenVT GPRNoX0:$rd), simm5:$simm),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2), Cond, (i32 GPRNoX0:$rd), simm5:$simm)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm)>;
class QCILICCIPat<CondCode Cond, QCILICC Inst, DAGOperand InTyImm>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), InTyImm:$imm, Cond)), simm5:$simm, (XLenVT GPRNoX0:$rd)),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond, simm5:$simm, (i32 GPRNoX0:$rd))),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, simm5:$simm)>;
class QCILICCIPatInv<CondCode Cond, QCILICC Inst, DAGOperand InTyImm>
- : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), InTyImm:$imm, Cond)), (XLenVT GPRNoX0:$rd), simm5:$simm),
+ : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), InTyImm:$imm, Cond, (i32 GPRNoX0:$rd), simm5:$simm)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, simm5:$simm)>;
// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.
@@ -1525,79 +1525,69 @@ let Predicates = [HasVendorXqciint, IsRV32] in
def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
let Predicates = [HasVendorXqcicm, IsRV32] in {
-def : Pat<(select (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rd),(i32 GPRNoX0:$rs3)),
- (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, (i32 0), GPRNoX0:$rs3)>;
+def : QCIMVCCPat<SETEQ, QC_MVEQ>;
+def : QCIMVCCPat<SETNE, QC_MVNE>;
+def : QCIMVCCPat<SETLT, QC_MVLT>;
+def : QCIMVCCPat<SETULT, QC_MVLTU>;
-def : QCIMVCCPat <SETEQ, QC_MVEQ>;
-def : QCIMVCCPat <SETNE, QC_MVNE>;
-def : QCIMVCCPat <SETLT, QC_MVLT>;
-def : QCIMVCCPat <SETULT, QC_MVLTU>;
-
-def : QCIMVCCIPat <SETLT, QC_MVLTI, simm5>;
-def : QCIMVCCIPat <SETULT, QC_MVLTUI, uimm5>;
+def : QCIMVCCIPat<SETLT, QC_MVLTI, simm5>;
+def : QCIMVCCIPat<SETULT, QC_MVLTUI, uimm5>;
}
// Prioritize Xqcics over these patterns.
let Predicates = [HasVendorXqcicm, NoVendorXqcics, IsRV32] in {
-def : QCIMVCCIPat <SETEQ, QC_MVEQI, simm5>;
-def : QCIMVCCIPat <SETNE, QC_MVNEI, simm5>;
+def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5>;
+def : QCIMVCCIPat<SETNE, QC_MVNEI, simm5>;
}
-let Predicates = [HasVendorXqcicli, HasVendorXqcicsOrXqcicm, IsRV32] in {
-def : QCILICCPat <SETEQ, QC_LIEQ>;
-def : QCILICCPat <SETNE, QC_LINE>;
-def : QCILICCPat <SETLT, QC_LILT>;
-def : QCILICCPat <SETGE, QC_LIGE>;
-def : QCILICCPat <SETULT, QC_LILTU>;
-def : QCILICCPat <SETUGE, QC_LIGEU>;
-
-def : QCILICCIPat <SETEQ, QC_LIEQI, simm5>;
-def : QCILICCIPat <SETNE, QC_LINEI, simm5>;
-def : QCILICCIPat <SETLT, QC_LILTI, simm5>;
-def : QCILICCIPat <SETGE, QC_LIGEI, simm5>;
-def : QCILICCIPat <SETULT, QC_LILTUI, uimm5>;
-def : QCILICCIPat <SETUGE, QC_LIGEUI, uimm5>;
-
-def : QCILICCPatInv <SETNE, QC_LIEQ>;
-def : QCILICCPatInv <SETEQ, QC_LINE>;
-def : QCILICCPatInv <SETGE, QC_LILT>;
-def : QCILICCPatInv <SETLT, QC_LIGE>;
-def : QCILICCPatInv <SETUGE, QC_LILTU>;
-def : QCILICCPatInv <SETULT, QC_LIGEU>;
-
-def : QCILICCIPatInv <SETNE, QC_LIEQI, simm5>;
-def : QCILICCIPatInv <SETEQ, QC_LINEI, simm5>;
-def : QCILICCIPatInv <SETGE, QC_LILTI, simm5>;
-def : QCILICCIPatInv <SETLT, QC_LIGEI, simm5>;
-def : QCILICCIPatInv <SETUGE, QC_LILTUI, uimm5>;
-def : QCILICCIPatInv <SETULT, QC_LIGEUI, uimm5>;
+let Predicates = [HasVendorXqcicli, IsRV32] in {
+def : QCILICCPat<SETEQ, QC_LIEQ>;
+def : QCILICCPat<SETNE, QC_LINE>;
+def : QCILICCPat<SETLT, QC_LILT>;
+def : QCILICCPat<SETGE, QC_LIGE>;
+def : QCILICCPat<SETULT, QC_LILTU>;
+def : QCILICCPat<SETUGE, QC_LIGEU>;
+
+def : QCILICCIPat<SETEQ, QC_LIEQI, simm5>;
+def : QCILICCIPat<SETNE, QC_LINEI, simm5>;
+def : QCILICCIPat<SETLT, QC_LILTI, simm5>;
+def : QCILICCIPat<SETGE, QC_LIGEI, simm5>;
+def : QCILICCIPat<SETULT, QC_LILTUI, uimm5>;
+def : QCILICCIPat<SETUGE, QC_LIGEUI, uimm5>;
+
+def : QCILICCPatInv<SETNE, QC_LIEQ>;
+def : QCILICCPatInv<SETEQ, QC_LINE>;
+def : QCILICCPatInv<SETGE, QC_LILT>;
+def : QCILICCPatInv<SETLT, QC_LIGE>;
+def : QCILICCPatInv<SETUGE, QC_LILTU>;
+def : QCILICCPatInv<SETULT, QC_LIGEU>;
+
+def : QCILICCIPatInv<SETNE, QC_LIEQI, simm5>;
+def : QCILICCIPatInv<SETEQ, QC_LINEI, simm5>;
+def : QCILICCIPatInv<SETGE, QC_LILTI, simm5>;
+def : QCILICCIPatInv<SETLT, QC_LIGEI, simm5>;
+def : QCILICCIPatInv<SETUGE, QC_LILTUI, uimm5>;
+def : QCILICCIPatInv<SETULT, QC_LIGEUI, uimm5>;
}
let Predicates = [HasVendorXqcics, IsRV32] in {
-def : Pat<(select (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs2),(i32 GPRNoX0:$rs3)),
- (QC_SELECTNEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
-def : Pat<(select (i32 GPRNoX0:$rd), (i32 GPRNoX0:$rs2), simm5:$simm2),
- (QC_SELECTINEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
-def : Pat<(select (i32 GPRNoX0:$rd), simm5:$simm2,(i32 GPRNoX0:$rs2)),
- (QC_SELECTIEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
-
-def : QCISELECTCCIPat <SETEQ, QC_SELECTEQI>;
-def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
+def : QCISELECTCCIPat<SETEQ, QC_SELECTEQI>;
+def : QCISELECTCCIPat<SETNE, QC_SELECTNEI>;
-def : QCISELECTICCIPat <SETEQ, QC_SELECTIEQI>;
-def : QCISELECTICCIPat <SETNE, QC_SELECTINEI>;
+def : QCISELECTICCIPat<SETEQ, QC_SELECTIEQI>;
+def : QCISELECTICCIPat<SETNE, QC_SELECTINEI>;
-def : QCISELECTICCIPatInv <SETEQ, QC_SELECTINEI>;
-def : QCISELECTICCIPatInv <SETNE, QC_SELECTIEQI>;
+def : QCISELECTICCIPatInv<SETEQ, QC_SELECTINEI>;
+def : QCISELECTICCIPatInv<SETNE, QC_SELECTIEQI>;
-def : QCISELECTICCPat <SETEQ, QC_SELECTIEQ>;
-def : QCISELECTICCPat <SETNE, QC_SELECTINE>;
+def : QCISELECTICCPat<SETEQ, QC_SELECTIEQ>;
+def : QCISELECTICCPat<SETNE, QC_SELECTINE>;
-def : QCISELECTICCPatInv <SETEQ, QC_SELECTINE>;
-def : QCISELECTICCPatInv <SETNE, QC_SELECTIEQ>;
+def : QCISELECTICCPatInv<SETEQ, QC_SELECTINE>;
+def : QCISELECTICCPatInv<SETNE, QC_SELECTIEQ>;
-def : QCISELECTIICCPat <SETEQ, QC_SELECTIIEQ>;
-def : QCISELECTIICCPat <SETNE, QC_SELECTIINE>;
+def : QCISELECTIICCPat<SETEQ, QC_SELECTIIEQ>;
+def : QCISELECTIICCPat<SETNE, QC_SELECTIINE>;
} // Predicates = [HasVendorXqcics, IsRV32]
let Predicates = [HasVendorXqcilsm, IsRV32] in {
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index 59f4d95f45acc..d8b22186e29b8 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -32,15 +32,22 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
;
; RV32-XQCICM-LABEL: select_i32_trunc:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32-XQCICM-NEXT: andi a3, a0, 1
; RV32-XQCICM-NEXT: mv a0, a1
+; RV32-XQCICM-NEXT: bnez a3, .LBB0_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: .LBB0_2:
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_trunc:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: andi a0, a0, 1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32-XQCICS-NEXT: andi a3, a0, 1
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: bnez a3, .LBB0_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a0, a2
+; RV32-XQCICS-NEXT: .LBB0_2:
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_trunc:
@@ -83,15 +90,22 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
;
; RV32-XQCICM-LABEL: select_i32_param:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32-XQCICM-NEXT: andi a3, a0, 1
; RV32-XQCICM-NEXT: mv a0, a1
+; RV32-XQCICM-NEXT: bnez a3, .LBB1_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: .LBB1_2:
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_param:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: andi a0, a0, 1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32-XQCICS-NEXT: andi a3, a0, 1
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: bnez a3, .LBB1_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a0, a2
+; RV32-XQCICS-NEXT: .LBB1_2:
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_param:
@@ -138,9 +152,11 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32-XQCICS-LABEL: select_i32_eq:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: xor a0, a0, a1
-; RV32-XQCICS-NEXT: seqz a0, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: beq a0, a1, .LBB2_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB2_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_eq:
@@ -187,9 +203,11 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
;
; RV32-XQCICS-LABEL: select_i32_ne:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: xor a0, a0, a1
-; RV32-XQCICS-NEXT: snez a0, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: bne a0, a1, .LBB3_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB3_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ne:
@@ -236,8 +254,11 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_ugt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: bltu a1, a0, .LBB4_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB4_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ugt:
@@ -278,14 +299,20 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_uge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32-XQCICM-NEXT: bgeu a0, a1, .LBB5_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a2, a3
+; RV32-XQCICM-NEXT: .LBB5_2:
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_uge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bgeu a0, a1, .LBB5_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB5_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_uge:
@@ -332,8 +359,11 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_ult:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: bltu a0, a1, .LBB6_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB6_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ult:
@@ -374,14 +404,20 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_ule:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32-XQCICM-NEXT: bgeu a1, a0, .LBB7_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a2, a3
+; RV32-XQCICM-NEXT: .LBB7_2:
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ule:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bgeu a1, a0, .LBB7_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB7_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ule:
@@ -428,8 +464,11 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_sgt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: blt a1, a0, .LBB8_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB8_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sgt:
@@ -470,14 +509,20 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32-XQCICM-NEXT: bge a0, a1, .LBB9_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a2, a3
+; RV32-XQCICM-NEXT: .LBB9_2:
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bge a0, a1, .LBB9_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB9_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sge:
@@ -524,8 +569,11 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICS-LABEL: select_i32_slt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
+; RV32-XQCICS-NEXT: blt a0, a1, .LBB10_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB10_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_slt:
@@ -566,14 +614,20 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sle:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32-XQCICM-NEXT: bge a1, a0, .LBB11_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a2, a3
+; RV32-XQCICM-NEXT: .LBB11_2:
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sle:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
+; RV32-XQCICS-NEXT: bge a1, a0, .LBB11_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a2, a3
+; RV32-XQCICS-NEXT: .LBB11_2:
+; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sle:
@@ -620,18 +674,25 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-LABEL: select_i64_trunc:
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: mv a1, a3
-; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a5
+; RV32-XQCICM-NEXT: andi a3, a0, 1
; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: bnez a3, .LBB12_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: .LBB12_2:
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_trunc:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: andi a1, a0, 1
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a3, a5
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a4
+; RV32-XQCICS-NEXT: mv a1, a3
+; RV32-XQCICS-NEXT: andi a3, a0, 1
+; RV32-XQCICS-NEXT: mv a0, a2
+; RV32-XQCICS-NEXT: bnez a3, .LBB12_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: .LBB12_2:
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_trunc:
@@ -678,20 +739,26 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICM-LABEL: select_i64_param:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: andi a0, a0, 1
-; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a3
-; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4
+; RV32-XQCICM-NEXT: andi a5, a0, 1
; RV32-XQCICM-NEXT: mv a0, a1
+; RV32-XQCICM-NEXT: bnez a5, .LBB13_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a3
+; RV32-XQCICM-NEXT: mv a2, a4
+; RV32-XQCICM-NEXT: .LBB13_2:
; RV32-XQCICM-NEXT: mv a1, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_param:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a5, a0, 1
-; RV32-XQCICS-NEXT: mv a0, a5
-; RV32-XQCICS-NEXT: qc.selectnei a5, 0, a2, a4
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a3
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: bnez a5, .LBB13_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a0, a3
+; RV32-XQCICS-NEXT: mv a2, a4
+; RV32-XQCICS-NEXT: .LBB13_2:
+; RV32-XQCICS-NEXT: mv a1, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_param:
@@ -743,11 +810,14 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: xor a1, a1, a3
; RV32-XQCICM-NEXT: xor a0, a0, a2
-; RV32-XQCICM-NEXT: or a0, a0, a1
-; RV32-XQCICM-NEXT: qc.mveqi a6, a0, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a0, 0, a5
+; RV32-XQCICM-NEXT: or a1, a1, a0
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: beqz a1, .LBB14_2
+; RV32-XQCICM-NEXT: # %bb.1:
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB14_2:
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_eq:
@@ -755,9 +825,13 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: xor a0, a0, a2
; RV32-XQCICS-NEXT: or a1, a0, a1
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: beqz a1, .LBB14_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a0, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB14_2:
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_eq:
@@ -809,11 +883,14 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: xor a1, a1, a3
; RV32-XQCICM-NEXT: xor a0, a0, a2
-; RV32-XQCICM-NEXT: or a0, a0, a1
-; RV32-XQCICM-NEXT: qc.mvnei a6, a0, 0, a4
-; RV32-XQCICM-NEXT: qc.mvnei a7, a0, 0, a5
+; RV32-XQCICM-NEXT: or a1, a1, a0
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: bnez a1, .LBB15_2
+; RV32-XQCICM-NEXT: # %bb.1:
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB15_2:
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ne:
@@ -821,9 +898,13 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: xor a0, a0, a2
; RV32-XQCICS-NEXT: or a1, a0, a1
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: bnez a1, .LBB15_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: mv a0, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB15_2:
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ne:
@@ -881,22 +962,31 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: sltu a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: bnez a2, .LBB16_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB16_2:
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ugt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a3, a1
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB16_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a0, a3, a1
+; RV32-XQCICS-NEXT: beqz a0, .LBB16_3
+; RV32-XQCICS-NEXT: j .LBB16_4
+; RV32-XQCICS-NEXT: .LBB16_2:
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: bnez a0, .LBB16_4
+; RV32-XQCICS-NEXT: .LBB16_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB16_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ugt:
@@ -954,22 +1044,31 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: sltu a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: beqz a2, .LBB17_2
+; RV32-XQCICM-NEXT: # %bb.1:
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB17_2:
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_uge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a1, a3
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB17_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a0, a1, a3
+; RV32-XQCICS-NEXT: bnez a0, .LBB17_3
+; RV32-XQCICS-NEXT: j .LBB17_4
+; RV32-XQCICS-NEXT: .LBB17_2:
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: beqz a0, .LBB17_4
+; RV32-XQCICS-NEXT: .LBB17_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB17_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_uge:
@@ -1027,22 +1126,31 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: sltu a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: bnez a2, .LBB18_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB18_2:
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ult:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a1, a3
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB18_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a0, a1, a3
+; RV32-XQCICS-NEXT: beqz a0, .LBB18_3
+; RV32-XQCICS-NEXT: j .LBB18_4
+; RV32-XQCICS-NEXT: .LBB18_2:
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: bnez a0, .LBB18_4
+; RV32-XQCICS-NEXT: .LBB18_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB18_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ult:
@@ -1100,22 +1208,31 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: sltu a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: beqz a2, .LBB19_2
+; RV32-XQCICM-NEXT: # %bb.1:
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB19_2:
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ule:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: sltu t0, a3, a1
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB19_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: sltu a0, a3, a1
+; RV32-XQCICS-NEXT: bnez a0, .LBB19_3
+; RV32-XQCICS-NEXT: j .LBB19_4
+; RV32-XQCICS-NEXT: .LBB19_2:
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: beqz a0, .LBB19_4
+; RV32-XQCICS-NEXT: .LBB19_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB19_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ule:
@@ -1173,22 +1290,31 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: slt a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: bnez a2, .LBB20_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB20_2:
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sgt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a3, a1
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB20_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a0, a3, a1
+; RV32-XQCICS-NEXT: beqz a0, .LBB20_3
+; RV32-XQCICS-NEXT: j .LBB20_4
+; RV32-XQCICS-NEXT: .LBB20_2:
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: bnez a0, .LBB20_4
+; RV32-XQCICS-NEXT: .LBB20_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB20_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sgt:
@@ -1246,22 +1372,31 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: slt a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: beqz a2, .LBB21_2
+; RV32-XQCICM-NEXT: # %bb.1:
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB21_2:
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sge:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a1, a3
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB21_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a0, a1, a3
+; RV32-XQCICS-NEXT: bnez a0, .LBB21_3
+; RV32-XQCICS-NEXT: j .LBB21_4
+; RV32-XQCICS-NEXT: .LBB21_2:
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: beqz a0, .LBB21_4
+; RV32-XQCICS-NEXT: .LBB21_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB21_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sge:
@@ -1319,22 +1454,31 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: slt a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a6
-; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a7
; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: bnez a2, .LBB22_2
+; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: mv a0, a6
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB22_2:
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_slt:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a1, a3
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB22_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a0, a1, a3
+; RV32-XQCICS-NEXT: beqz a0, .LBB22_3
+; RV32-XQCICS-NEXT: j .LBB22_4
+; RV32-XQCICS-NEXT: .LBB22_2:
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: bnez a0, .LBB22_4
+; RV32-XQCICS-NEXT: .LBB22_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB22_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_slt:
@@ -1392,22 +1536,31 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: slt a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
-; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32-XQCICM-NEXT: mv a0, a4
+; RV32-XQCICM-NEXT: beqz a2, .LBB23_2
+; RV32-XQCICM-NEXT: # %bb.1:
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a1, a7
+; RV32-XQCICM-NEXT: mv a5, a7
+; RV32-XQCICM-NEXT: .LBB23_2:
+; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sle:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: slt t0, a3, a1
+; RV32-XQCICS-NEXT: beq a1, a3, .LBB23_2
+; RV32-XQCICS-NEXT: # %bb.1:
+; RV32-XQCICS-NEXT: slt a0, a3, a1
+; RV32-XQCICS-NEXT: bnez a0, .LBB23_3
+; RV32-XQCICS-NEXT: j .LBB23_4
+; RV32-XQCICS-NEXT: .LBB23_2:
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: xor a1, a1, a3
-; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
+; RV32-XQCICS-NEXT: beqz a0, .LBB23_4
+; RV32-XQCICS-NEXT: .LBB23_3:
+; RV32-XQCICS-NEXT: mv a4, a6
+; RV32-XQCICS-NEXT: mv a5, a7
+; RV32-XQCICS-NEXT: .LBB23_4:
+; RV32-XQCICS-NEXT: mv a0, a4
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sle:
diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll
index b0d51429556ef..fca3f1736cbe2 100644
--- a/llvm/test/CodeGen/RISCV/xqcicli.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicli.ll
@@ -307,7 +307,8 @@ define i32 @select_cc_example_sgei(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_sgei:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 12, 11
+; RV32IXQCICLI-NEXT: li a2, 11
+; RV32IXQCICLI-NEXT: qc.lilt a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
@@ -347,7 +348,8 @@ define i32 @select_cc_example_ugei(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ugei:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 12, 11
+; RV32IXQCICLI-NEXT: li a2, 11
+; RV32IXQCICLI-NEXT: qc.liltu a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
@@ -407,7 +409,8 @@ define i32 @select_cc_example_slti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_slti_c1:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 13, 11
+; RV32IXQCICLI-NEXT: li a2, 12
+; RV32IXQCICLI-NEXT: qc.lilt a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
@@ -447,7 +450,8 @@ define i32 @select_cc_example_ulti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ulti_c1:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 13, 11
+; RV32IXQCICLI-NEXT: li a2, 12
+; RV32IXQCICLI-NEXT: qc.liltu a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
@@ -527,7 +531,8 @@ define i32 @select_cc_example_slti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_slti_c2:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 13, 11
+; RV32IXQCICLI-NEXT: li a2, 12
+; RV32IXQCICLI-NEXT: qc.lige a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
@@ -567,7 +572,8 @@ define i32 @select_cc_example_ulti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ulti_c2:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 13, 11
+; RV32IXQCICLI-NEXT: li a2, 12
+; RV32IXQCICLI-NEXT: qc.ligeu a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
@@ -667,7 +673,8 @@ define i32 @select_cc_example_sgei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_sgei_c3:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 12, 11
+; RV32IXQCICLI-NEXT: li a2, 11
+; RV32IXQCICLI-NEXT: qc.lige a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
@@ -707,7 +714,8 @@ define i32 @select_cc_example_ugei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ugei_c3:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 12, 11
+; RV32IXQCICLI-NEXT: li a2, 11
+; RV32IXQCICLI-NEXT: qc.ligeu a0, a2, a1, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index 56fc864f8ccdc..612e6de1ca976 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -18,9 +18,12 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_example:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: andi a0, a0, 1
-; RV32IXQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCICM-NEXT: andi a3, a0, 1
; RV32IXQCICM-NEXT: mv a0, a1
+; RV32IXQCICM-NEXT: bnez a3, .LBB0_2
+; RV32IXQCICM-NEXT: # %bb.1: # %entry
+; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: .LBB0_2: # %entry
; RV32IXQCICM-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
@@ -151,8 +154,9 @@ define i32 @select_cc_example_slt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 11
+; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp slt i32 11, %a
@@ -195,8 +199,9 @@ define i32 @select_cc_example_sle1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 10
+; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp sle i32 11, %a
@@ -217,8 +222,9 @@ define i32 @select_cc_example_sgt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 11
+; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 11
@@ -261,8 +267,9 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 10
+; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp sge i32 %a, 11
@@ -327,8 +334,9 @@ define i32 @select_cc_example_ule1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 10
+; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp ule i32 11, %a
@@ -349,8 +357,9 @@ define i32 @select_cc_example_ugt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 11
+; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, 11
@@ -415,8 +424,9 @@ define i32 @select_cc_example_ult1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 11
+; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp ult i32 11, %a
@@ -437,8 +447,9 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: li a1, 10
+; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp uge i32 %a, 11
@@ -543,7 +554,10 @@ define i32 @select_cc_example_sge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a2, a0, a1, a3
+; RV32IXQCICM-NEXT: bge a0, a1, .LBB24_2
+; RV32IXQCICM-NEXT: # %bb.1: # %entry
+; RV32IXQCICM-NEXT: mv a2, a3
+; RV32IXQCICM-NEXT: .LBB24_2: # %entry
; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
entry:
@@ -585,7 +599,10 @@ define i32 @select_cc_example_sle_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a2, a1, a0, a3
+; RV32IXQCICM-NEXT: bge a1, a0, .LBB26_2
+; RV32IXQCICM-NEXT: # %bb.1: # %entry
+; RV32IXQCICM-NEXT: mv a2, a3
+; RV32IXQCICM-NEXT: .LBB26_2: # %entry
; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
entry:
@@ -648,7 +665,10 @@ define i32 @select_cc_example_uge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a2, a0, a1, a3
+; RV32IXQCICM-NEXT: bgeu a0, a1, .LBB29_2
+; RV32IXQCICM-NEXT: # %bb.1: # %entry
+; RV32IXQCICM-NEXT: mv a2, a3
+; RV32IXQCICM-NEXT: .LBB29_2: # %entry
; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
entry:
@@ -669,7 +689,10 @@ define i32 @select_cc_example_ule_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltu a2, a1, a0, a3
+; RV32IXQCICM-NEXT: bgeu a1, a0, .LBB30_2
+; RV32IXQCICM-NEXT: # %bb.1: # %entry
+; RV32IXQCICM-NEXT: mv a2, a3
+; RV32IXQCICM-NEXT: .LBB30_2: # %entry
; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
entry:
>From a5ae70600c120aea11e06f793cfc5ca301c688f0 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Mon, 11 Aug 2025 22:30:52 -0700
Subject: [PATCH 02/14] Re-add GE/UGE Patterns, add C++ for CC modification
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 14 ++++++
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 4 ++
llvm/test/CodeGen/RISCV/select-cond.ll | 28 ++++-------
llvm/test/CodeGen/RISCV/xqcicm.ll | 52 +++++++--------------
4 files changed, 42 insertions(+), 56 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6961df8ab723a..d942c1f71976d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2504,6 +2504,13 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
CC = ISD::SETGE;
return;
}
+ if (Subtarget.hasVendorXqcicm() && C != INT64_MAX && isInt<5>(C+1)) {
+ // We have a conditional move instruction for SETGE but not SETGT.
+ // Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
+ RHS = DAG.getSignedConstant(C+1, DL, RHS.getValueType());
+ CC = ISD::SETGE;
+ return;
+ }
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1)) {
// We have a branch immediate instruction for SETGE but not SETGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 16-bit signed immediate.
@@ -2522,6 +2529,13 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
}
break;
case ISD::SETUGT:
+ if (Subtarget.hasVendorXqcicm() && C != INT64_MAX && isUInt<5>(C + 1)) {
+ // We have a conditional move instruction for SETUGE but not SETUGT.
+ // Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
+ RHS = DAG.getConstant(C + 1, DL, RHS.getValueType());
+ CC = ISD::SETUGE;
+ return;
+ }
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1) &&
C != -1) {
// We have a branch immediate instruction for SETUGE but not SETUGT.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 59738a979c540..67c921fd5ebac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1529,9 +1529,13 @@ def : QCIMVCCPat<SETEQ, QC_MVEQ>;
def : QCIMVCCPat<SETNE, QC_MVNE>;
def : QCIMVCCPat<SETLT, QC_MVLT>;
def : QCIMVCCPat<SETULT, QC_MVLTU>;
+def : QCIMVCCPat<SETGE, QC_MVGE>;
+def : QCIMVCCPat<SETUGE, QC_MVGEU>;
def : QCIMVCCIPat<SETLT, QC_MVLTI, simm5>;
def : QCIMVCCIPat<SETULT, QC_MVLTUI, uimm5>;
+def : QCIMVCCIPat<SETGE, QC_MVGEI, simm5>;
+def : QCIMVCCIPat<SETUGE, QC_MVGEUI, uimm5>;
}
// Prioritize Xqcics over these patterns.
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index d8b22186e29b8..00d76b0b4c77b 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -299,11 +299,8 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_uge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: bgeu a0, a1, .LBB5_2
-; RV32-XQCICM-NEXT: # %bb.1:
-; RV32-XQCICM-NEXT: mv a2, a3
-; RV32-XQCICM-NEXT: .LBB5_2:
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_uge:
@@ -404,11 +401,8 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_ule:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: bgeu a1, a0, .LBB7_2
-; RV32-XQCICM-NEXT: # %bb.1:
-; RV32-XQCICM-NEXT: mv a2, a3
-; RV32-XQCICM-NEXT: .LBB7_2:
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ule:
@@ -509,11 +503,8 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sge:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: bge a0, a1, .LBB9_2
-; RV32-XQCICM-NEXT: # %bb.1:
-; RV32-XQCICM-NEXT: mv a2, a3
-; RV32-XQCICM-NEXT: .LBB9_2:
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvge a3, a0, a1, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sge:
@@ -614,11 +605,8 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
;
; RV32-XQCICM-LABEL: select_i32_sle:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: bge a1, a0, .LBB11_2
-; RV32-XQCICM-NEXT: # %bb.1:
-; RV32-XQCICM-NEXT: mv a2, a3
-; RV32-XQCICM-NEXT: .LBB11_2:
-; RV32-XQCICM-NEXT: mv a0, a2
+; RV32-XQCICM-NEXT: qc.mvge a3, a1, a0, a2
+; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sle:
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index 612e6de1ca976..d1783ba351253 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -154,8 +154,7 @@ define i32 @select_cc_example_slt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 11
-; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -199,8 +198,7 @@ define i32 @select_cc_example_sle1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 10
-; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -222,8 +220,7 @@ define i32 @select_cc_example_sgt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 11
-; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -267,8 +264,7 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 10
-; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -334,8 +330,7 @@ define i32 @select_cc_example_ule1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 10
-; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -357,8 +352,7 @@ define i32 @select_cc_example_ugt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 11
-; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -424,8 +418,7 @@ define i32 @select_cc_example_ult1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 11
-; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -447,8 +440,7 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: li a1, 10
-; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
@@ -554,11 +546,8 @@ define i32 @select_cc_example_sge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: bge a0, a1, .LBB24_2
-; RV32IXQCICM-NEXT: # %bb.1: # %entry
-; RV32IXQCICM-NEXT: mv a2, a3
-; RV32IXQCICM-NEXT: .LBB24_2: # %entry
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvge a3, a0, a1, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp sge i32 %a, %b
@@ -599,11 +588,8 @@ define i32 @select_cc_example_sle_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: bge a1, a0, .LBB26_2
-; RV32IXQCICM-NEXT: # %bb.1: # %entry
-; RV32IXQCICM-NEXT: mv a2, a3
-; RV32IXQCICM-NEXT: .LBB26_2: # %entry
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvge a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp sle i32 %a, %b
@@ -665,11 +651,8 @@ define i32 @select_cc_example_uge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: bgeu a0, a1, .LBB29_2
-; RV32IXQCICM-NEXT: # %bb.1: # %entry
-; RV32IXQCICM-NEXT: mv a2, a3
-; RV32IXQCICM-NEXT: .LBB29_2: # %entry
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp uge i32 %a, %b
@@ -689,11 +672,8 @@ define i32 @select_cc_example_ule_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: bgeu a1, a0, .LBB30_2
-; RV32IXQCICM-NEXT: # %bb.1: # %entry
-; RV32IXQCICM-NEXT: mv a2, a3
-; RV32IXQCICM-NEXT: .LBB30_2: # %entry
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
entry:
%cmp = icmp ule i32 %a, %b
>From 985f6785a43451d6021b8fee6f1bda7d2f8cb9c5 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Mon, 11 Aug 2025 23:35:27 -0700
Subject: [PATCH 03/14] Add priority pattern for NE Zero
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 5 ++
llvm/test/CodeGen/RISCV/select-cond.ll | 83 +++++++--------------
llvm/test/CodeGen/RISCV/xqcicm.ll | 7 +-
3 files changed, 35 insertions(+), 60 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 67c921fd5ebac..5124f72222c2c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1540,6 +1540,11 @@ def : QCIMVCCIPat<SETUGE, QC_MVGEUI, uimm5>;
// Prioritize Xqcics over these patterns.
let Predicates = [HasVendorXqcicm, NoVendorXqcics, IsRV32] in {
+// (SELECT X, Y, Z) is canonicalised to `riscv_selectcc x, 0, NE, y, z)`.
+// This exists to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETNE, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
+ (QC_MVNEI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
+
def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5>;
def : QCIMVCCIPat<SETNE, QC_MVNEI, simm5>;
}
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index 00d76b0b4c77b..17d687d7e723b 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -32,12 +32,9 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
;
; RV32-XQCICM-LABEL: select_i32_trunc:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: andi a3, a0, 1
-; RV32-XQCICM-NEXT: mv a0, a1
-; RV32-XQCICM-NEXT: bnez a3, .LBB0_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: andi a0, a0, 1
+; RV32-XQCICM-NEXT: qc.mvnei a2, a0, 0, a1
; RV32-XQCICM-NEXT: mv a0, a2
-; RV32-XQCICM-NEXT: .LBB0_2:
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_trunc:
@@ -90,12 +87,9 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
;
; RV32-XQCICM-LABEL: select_i32_param:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: andi a3, a0, 1
-; RV32-XQCICM-NEXT: mv a0, a1
-; RV32-XQCICM-NEXT: bnez a3, .LBB1_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: andi a0, a0, 1
+; RV32-XQCICM-NEXT: qc.mvnei a2, a0, 0, a1
; RV32-XQCICM-NEXT: mv a0, a2
-; RV32-XQCICM-NEXT: .LBB1_2:
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_param:
@@ -661,14 +655,11 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICM-LABEL: select_i64_trunc:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: mv a1, a3
-; RV32-XQCICM-NEXT: andi a3, a0, 1
-; RV32-XQCICM-NEXT: mv a0, a2
-; RV32-XQCICM-NEXT: bnez a3, .LBB12_2
-; RV32-XQCICM-NEXT: # %bb.1:
-; RV32-XQCICM-NEXT: mv a0, a4
; RV32-XQCICM-NEXT: mv a1, a5
-; RV32-XQCICM-NEXT: .LBB12_2:
+; RV32-XQCICM-NEXT: andi a0, a0, 1
+; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32-XQCICM-NEXT: qc.mvnei a1, a0, 0, a3
+; RV32-XQCICM-NEXT: mv a0, a4
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_trunc:
@@ -727,14 +718,11 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICM-LABEL: select_i64_param:
; RV32-XQCICM: # %bb.0:
-; RV32-XQCICM-NEXT: andi a5, a0, 1
-; RV32-XQCICM-NEXT: mv a0, a1
-; RV32-XQCICM-NEXT: bnez a5, .LBB13_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: andi a0, a0, 1
+; RV32-XQCICM-NEXT: qc.mvnei a3, a0, 0, a1
+; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a2
; RV32-XQCICM-NEXT: mv a0, a3
-; RV32-XQCICM-NEXT: mv a2, a4
-; RV32-XQCICM-NEXT: .LBB13_2:
-; RV32-XQCICM-NEXT: mv a1, a2
+; RV32-XQCICM-NEXT: mv a1, a4
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_param:
@@ -871,14 +859,11 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: xor a1, a1, a3
; RV32-XQCICM-NEXT: xor a0, a0, a2
-; RV32-XQCICM-NEXT: or a1, a1, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: bnez a1, .LBB15_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: or a0, a0, a1
+; RV32-XQCICM-NEXT: qc.mvnei a6, a0, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a0, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB15_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ne:
@@ -950,13 +935,10 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: sltu a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: bnez a2, .LBB16_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB16_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ugt:
@@ -1114,13 +1096,10 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: sltu a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: bnez a2, .LBB18_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB18_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ult:
@@ -1278,13 +1257,10 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: slt a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: bnez a2, .LBB20_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB20_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sgt:
@@ -1442,13 +1418,10 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: slt a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: bnez a2, .LBB22_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mvnei a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB22_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_slt:
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index d1783ba351253..beb2c6aff0053 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -18,12 +18,9 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_example:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: andi a3, a0, 1
-; RV32IXQCICM-NEXT: mv a0, a1
-; RV32IXQCICM-NEXT: bnez a3, .LBB0_2
-; RV32IXQCICM-NEXT: # %bb.1: # %entry
+; RV32IXQCICM-NEXT: andi a0, a0, 1
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 0, a1
; RV32IXQCICM-NEXT: mv a0, a2
-; RV32IXQCICM-NEXT: .LBB0_2: # %entry
; RV32IXQCICM-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
>From ccf5a1954eac2403ab8601c3b8a2af07d662648b Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Mon, 11 Aug 2025 23:56:13 -0700
Subject: [PATCH 04/14] C++ for CC modification with xqcili
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 ++++--
llvm/test/CodeGen/RISCV/xqcicli.ll | 4 +---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d942c1f71976d..f092d59151300 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2504,7 +2504,8 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
CC = ISD::SETGE;
return;
}
- if (Subtarget.hasVendorXqcicm() && C != INT64_MAX && isInt<5>(C+1)) {
+ if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcili()) &&
+ C != INT64_MAX && isInt<5>(C + 1)) {
// We have a conditional move instruction for SETGE but not SETGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
RHS = DAG.getSignedConstant(C+1, DL, RHS.getValueType());
@@ -2529,7 +2530,8 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
}
break;
case ISD::SETUGT:
- if (Subtarget.hasVendorXqcicm() && C != INT64_MAX && isUInt<5>(C + 1)) {
+ if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcili()) &&
+ C != INT64_MAX && isUInt<5>(C + 1)) {
// We have a conditional move instruction for SETUGE but not SETUGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
RHS = DAG.getConstant(C + 1, DL, RHS.getValueType());
diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll
index fca3f1736cbe2..19dfad3ebe878 100644
--- a/llvm/test/CodeGen/RISCV/xqcicli.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicli.ll
@@ -2,9 +2,7 @@
; Test that we are able to generate the Xqcicli instructions
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli,+experimental-xqcics -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=RV32IXQCICLI
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli,+experimental-xqcicm -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICLI
define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
>From e1cc25aa58161780ce0d55ab468835e5fea12789 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 00:18:37 -0700
Subject: [PATCH 05/14] NE 0 patterns for Xqcics
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 16 ++-
llvm/test/CodeGen/RISCV/select-cond.ll | 113 +++++++-------------
2 files changed, 54 insertions(+), 75 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 5124f72222c2c..2c2edff4f4e52 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1540,11 +1540,14 @@ def : QCIMVCCIPat<SETUGE, QC_MVGEUI, uimm5>;
// Prioritize Xqcics over these patterns.
let Predicates = [HasVendorXqcicm, NoVendorXqcics, IsRV32] in {
-// (SELECT X, Y, Z) is canonicalised to `riscv_selectcc x, 0, NE, y, z)`.
+// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
// This exists to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETNE, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
(QC_MVNEI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
+// def : Pat<(select (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rd),(i32 GPRNoX0:$rs3)),
+// (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, (i32 0), GPRNoX0:$rs3)>;
+
def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5>;
def : QCIMVCCIPat<SETNE, QC_MVNEI, simm5>;
}
@@ -1580,6 +1583,17 @@ def : QCILICCIPatInv<SETULT, QC_LIGEUI, uimm5>;
}
let Predicates = [HasVendorXqcics, IsRV32] in {
+// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
+// These exist to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
+
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
+ (QC_SELECTNEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), simm5:$simm2)),
+ (QC_SELECTINEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, simm5:$simm2, (i32 GPRNoX0:$rs2))),
+ (QC_SELECTIEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
+
def : QCISELECTCCIPat<SETEQ, QC_SELECTEQI>;
def : QCISELECTCCIPat<SETNE, QC_SELECTNEI>;
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index 17d687d7e723b..c1f78bc4ee1d1 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -39,12 +39,8 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
;
; RV32-XQCICS-LABEL: select_i32_trunc:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: andi a3, a0, 1
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: bnez a3, .LBB0_2
-; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: mv a0, a2
-; RV32-XQCICS-NEXT: .LBB0_2:
+; RV32-XQCICS-NEXT: andi a0, a0, 1
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_trunc:
@@ -94,12 +90,8 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
;
; RV32-XQCICS-LABEL: select_i32_param:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: andi a3, a0, 1
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: bnez a3, .LBB1_2
-; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: mv a0, a2
-; RV32-XQCICS-NEXT: .LBB1_2:
+; RV32-XQCICS-NEXT: andi a0, a0, 1
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_param:
@@ -664,14 +656,10 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_trunc:
; RV32-XQCICS: # %bb.0:
-; RV32-XQCICS-NEXT: mv a1, a3
-; RV32-XQCICS-NEXT: andi a3, a0, 1
-; RV32-XQCICS-NEXT: mv a0, a2
-; RV32-XQCICS-NEXT: bnez a3, .LBB12_2
-; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
-; RV32-XQCICS-NEXT: .LBB12_2:
+; RV32-XQCICS-NEXT: andi a1, a0, 1
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a3, a5
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a4
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_trunc:
@@ -728,13 +716,10 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-LABEL: select_i64_param:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a5, a0, 1
-; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: bnez a5, .LBB13_2
-; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: mv a0, a3
-; RV32-XQCICS-NEXT: mv a2, a4
-; RV32-XQCICS-NEXT: .LBB13_2:
-; RV32-XQCICS-NEXT: mv a1, a2
+; RV32-XQCICS-NEXT: mv a0, a5
+; RV32-XQCICS-NEXT: qc.selectnei a5, 0, a2, a4
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a3
+; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_param:
@@ -871,13 +856,9 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: xor a0, a0, a2
; RV32-XQCICS-NEXT: or a1, a0, a1
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: bnez a1, .LBB15_2
-; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: mv a0, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB15_2:
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ne:
@@ -945,18 +926,14 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB16_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: sltu a0, a3, a1
-; RV32-XQCICS-NEXT: beqz a0, .LBB16_3
-; RV32-XQCICS-NEXT: j .LBB16_4
+; RV32-XQCICS-NEXT: sltu a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB16_3
; RV32-XQCICS-NEXT: .LBB16_2:
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: bnez a0, .LBB16_4
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
; RV32-XQCICS-NEXT: .LBB16_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB16_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ugt:
@@ -1106,18 +1083,14 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB18_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: sltu a0, a1, a3
-; RV32-XQCICS-NEXT: beqz a0, .LBB18_3
-; RV32-XQCICS-NEXT: j .LBB18_4
+; RV32-XQCICS-NEXT: sltu a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB18_3
; RV32-XQCICS-NEXT: .LBB18_2:
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: bnez a0, .LBB18_4
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
; RV32-XQCICS-NEXT: .LBB18_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB18_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ult:
@@ -1267,18 +1240,14 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB20_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: slt a0, a3, a1
-; RV32-XQCICS-NEXT: beqz a0, .LBB20_3
-; RV32-XQCICS-NEXT: j .LBB20_4
+; RV32-XQCICS-NEXT: slt a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB20_3
; RV32-XQCICS-NEXT: .LBB20_2:
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: bnez a0, .LBB20_4
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
; RV32-XQCICS-NEXT: .LBB20_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB20_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sgt:
@@ -1428,18 +1397,14 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB22_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: slt a0, a1, a3
-; RV32-XQCICS-NEXT: beqz a0, .LBB22_3
-; RV32-XQCICS-NEXT: j .LBB22_4
+; RV32-XQCICS-NEXT: slt a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB22_3
; RV32-XQCICS-NEXT: .LBB22_2:
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: bnez a0, .LBB22_4
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
; RV32-XQCICS-NEXT: .LBB22_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB22_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_slt:
>From c29b99f2b6b5adf7d2384b3bdd1ea030fb18499a Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 11:06:51 -0700
Subject: [PATCH 06/14] clang-format
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f092d59151300..f96cd60950923 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2508,7 +2508,7 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
C != INT64_MAX && isInt<5>(C + 1)) {
// We have a conditional move instruction for SETGE but not SETGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
- RHS = DAG.getSignedConstant(C+1, DL, RHS.getValueType());
+ RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType());
CC = ISD::SETGE;
return;
}
>From 0ea487b1d8f4bee65b9bcfac7132a1458ee89660 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 20:49:52 -0700
Subject: [PATCH 07/14] Remove Unused Predicate
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a7329d201f880..0f8956e524c1b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1488,9 +1488,6 @@ def HasVendorXqcics
def NoVendorXqcics
: Predicate<"!Subtarget->hasVendorXqcics()">;
-def HasVendorXqcicsOrXqcicm
- : Predicate<"Subtarget->hasVendorXqcics() || Subtarget->hasVendorXqcicm()">;
-
def FeatureVendorXqcicsr
: RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">;
def HasVendorXqcicsr
>From ccc66425e87e194797c476a59b7b40216462b049 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 21:08:14 -0700
Subject: [PATCH 08/14] Typo in ISelLowering
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++--
llvm/test/CodeGen/RISCV/xqcicli.ll | 24 +++++++--------------
2 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 539bd6c326a68..0e0193326d94a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2504,7 +2504,7 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
CC = ISD::SETGE;
return;
}
- if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcili()) &&
+ if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcicli()) &&
C != INT64_MAX && isInt<5>(C + 1)) {
// We have a conditional move instruction for SETGE but not SETGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
@@ -2530,7 +2530,7 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
}
break;
case ISD::SETUGT:
- if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcili()) &&
+ if ((Subtarget.hasVendorXqcicm() || Subtarget.hasVendorXqcicli()) &&
C != INT64_MAX && isUInt<5>(C + 1)) {
// We have a conditional move instruction for SETUGE but not SETUGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 5-bit signed immediate.
diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll
index 19dfad3ebe878..fb34123e7ad2a 100644
--- a/llvm/test/CodeGen/RISCV/xqcicli.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicli.ll
@@ -305,8 +305,7 @@ define i32 @select_cc_example_sgei(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_sgei:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 11
-; RV32IXQCICLI-NEXT: qc.lilt a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
@@ -346,8 +345,7 @@ define i32 @select_cc_example_ugei(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ugei:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 11
-; RV32IXQCICLI-NEXT: qc.liltu a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
@@ -407,8 +405,7 @@ define i32 @select_cc_example_slti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_slti_c1:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 12
-; RV32IXQCICLI-NEXT: qc.lilt a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
@@ -448,8 +445,7 @@ define i32 @select_cc_example_ulti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ulti_c1:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 12
-; RV32IXQCICLI-NEXT: qc.liltu a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
@@ -529,8 +525,7 @@ define i32 @select_cc_example_slti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_slti_c2:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 12
-; RV32IXQCICLI-NEXT: qc.lige a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
@@ -570,8 +565,7 @@ define i32 @select_cc_example_ulti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ulti_c2:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 12
-; RV32IXQCICLI-NEXT: qc.ligeu a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
@@ -671,8 +665,7 @@ define i32 @select_cc_example_sgei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_sgei_c3:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 11
-; RV32IXQCICLI-NEXT: qc.lige a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
@@ -712,8 +705,7 @@ define i32 @select_cc_example_ugei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICLI-LABEL: select_cc_example_ugei_c3:
; RV32IXQCICLI: # %bb.0: # %entry
-; RV32IXQCICLI-NEXT: li a2, 11
-; RV32IXQCICLI-NEXT: qc.ligeu a0, a2, a1, 11
+; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
>From f3e5d233875fe9ed9329e22c7bd2bf9d54a415e9 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 21:44:00 -0700
Subject: [PATCH 09/14] Add SETEQ 0 Patterns
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 7 +-
llvm/test/CodeGen/RISCV/select-cond.ll | 121 +++++++-------------
2 files changed, 47 insertions(+), 81 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 2c2edff4f4e52..553120e3d9575 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1544,9 +1544,8 @@ let Predicates = [HasVendorXqcicm, NoVendorXqcics, IsRV32] in {
// This exists to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETNE, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
(QC_MVNEI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
-
-// def : Pat<(select (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rd),(i32 GPRNoX0:$rs3)),
-// (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, (i32 0), GPRNoX0:$rs3)>;
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETEQ, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
+ (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5>;
def : QCIMVCCIPat<SETNE, QC_MVNEI, simm5>;
@@ -1588,6 +1587,8 @@ let Predicates = [HasVendorXqcics, IsRV32] in {
def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
(QC_SELECTNEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETEQ, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
+ (QC_SELECTEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), simm5:$simm2)),
(QC_SELECTINEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index c1f78bc4ee1d1..6275d1a7eb84b 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -771,14 +771,11 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM: # %bb.0:
; RV32-XQCICM-NEXT: xor a1, a1, a3
; RV32-XQCICM-NEXT: xor a0, a0, a2
-; RV32-XQCICM-NEXT: or a1, a1, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: beqz a1, .LBB14_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: or a0, a0, a1
+; RV32-XQCICM-NEXT: qc.mveqi a6, a0, 0, a4
+; RV32-XQCICM-NEXT: qc.mveqi a7, a0, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB14_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_eq:
@@ -786,13 +783,9 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: xor a0, a0, a2
; RV32-XQCICS-NEXT: or a1, a0, a1
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: beqz a1, .LBB14_2
-; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: mv a0, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB14_2:
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_eq:
@@ -991,31 +984,24 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: sltu a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: beqz a2, .LBB17_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB17_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_uge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB17_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: sltu a0, a1, a3
-; RV32-XQCICS-NEXT: bnez a0, .LBB17_3
-; RV32-XQCICS-NEXT: j .LBB17_4
+; RV32-XQCICS-NEXT: sltu a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB17_3
; RV32-XQCICS-NEXT: .LBB17_2:
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: beqz a0, .LBB17_4
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
; RV32-XQCICS-NEXT: .LBB17_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB17_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_uge:
@@ -1148,31 +1134,24 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: sltu a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: beqz a2, .LBB19_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB19_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ule:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB19_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: sltu a0, a3, a1
-; RV32-XQCICS-NEXT: bnez a0, .LBB19_3
-; RV32-XQCICS-NEXT: j .LBB19_4
+; RV32-XQCICS-NEXT: sltu a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB19_3
; RV32-XQCICS-NEXT: .LBB19_2:
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: beqz a0, .LBB19_4
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
; RV32-XQCICS-NEXT: .LBB19_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB19_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ule:
@@ -1305,31 +1284,24 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a0, a2
; RV32-XQCICM-NEXT: slt a2, a1, a3
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: beqz a2, .LBB21_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB21_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB21_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: slt a0, a1, a3
-; RV32-XQCICS-NEXT: bnez a0, .LBB21_3
-; RV32-XQCICS-NEXT: j .LBB21_4
+; RV32-XQCICS-NEXT: slt a1, a1, a3
+; RV32-XQCICS-NEXT: j .LBB21_3
; RV32-XQCICS-NEXT: .LBB21_2:
-; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: beqz a0, .LBB21_4
+; RV32-XQCICS-NEXT: sltu a1, a0, a2
; RV32-XQCICS-NEXT: .LBB21_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB21_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sge:
@@ -1462,31 +1434,24 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: sltu a0, a2, a0
; RV32-XQCICM-NEXT: slt a2, a3, a1
; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a0
-; RV32-XQCICM-NEXT: mv a0, a4
-; RV32-XQCICM-NEXT: beqz a2, .LBB23_2
-; RV32-XQCICM-NEXT: # %bb.1:
+; RV32-XQCICM-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32-XQCICM-NEXT: qc.mveqi a7, a2, 0, a5
; RV32-XQCICM-NEXT: mv a0, a6
-; RV32-XQCICM-NEXT: mv a5, a7
-; RV32-XQCICM-NEXT: .LBB23_2:
-; RV32-XQCICM-NEXT: mv a1, a5
+; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sle:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: beq a1, a3, .LBB23_2
; RV32-XQCICS-NEXT: # %bb.1:
-; RV32-XQCICS-NEXT: slt a0, a3, a1
-; RV32-XQCICS-NEXT: bnez a0, .LBB23_3
-; RV32-XQCICS-NEXT: j .LBB23_4
+; RV32-XQCICS-NEXT: slt a1, a3, a1
+; RV32-XQCICS-NEXT: j .LBB23_3
; RV32-XQCICS-NEXT: .LBB23_2:
-; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: beqz a0, .LBB23_4
+; RV32-XQCICS-NEXT: sltu a1, a2, a0
; RV32-XQCICS-NEXT: .LBB23_3:
-; RV32-XQCICS-NEXT: mv a4, a6
-; RV32-XQCICS-NEXT: mv a5, a7
-; RV32-XQCICS-NEXT: .LBB23_4:
-; RV32-XQCICS-NEXT: mv a0, a4
-; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sle:
>From aac1b4c99cfcc0f059c126c73d3f40f1eb91cd30 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 22:16:51 -0700
Subject: [PATCH 10/14] More Coverage
---
llvm/test/CodeGen/RISCV/select-bare.ll | 14 ++
llvm/test/CodeGen/RISCV/select-cc.ll | 76 +++++++++
llvm/test/CodeGen/RISCV/select-cond.ll | 199 ++++++++++++++++++++++++
llvm/test/CodeGen/RISCV/select-const.ll | 138 ++++++++++++++++
llvm/test/CodeGen/RISCV/select.ll | 2 +
llvm/test/CodeGen/RISCV/xqcicli.ll | 182 ++++++++++++++++++++++
llvm/test/CodeGen/RISCV/xqcicm.ll | 191 +++++++++++++++++++++++
llvm/test/CodeGen/RISCV/xqcics.ll | 123 +++++++++++++++
8 files changed, 925 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll
index fc8eaa480b116..e6b742375df57 100644
--- a/llvm/test/CodeGen/RISCV/select-bare.ll
+++ b/llvm/test/CodeGen/RISCV/select-bare.ll
@@ -3,6 +3,8 @@
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select:
@@ -20,6 +22,12 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV64I-CCMOV-NEXT: andi a0, a0, 1
; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2
; RV64I-CCMOV-NEXT: ret
+;
+; RV32IXQCI-LABEL: bare_select:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
}
@@ -40,6 +48,12 @@ define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV64I-CCMOV-NEXT: andi a0, a0, 1
; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2
; RV64I-CCMOV-NEXT: ret
+;
+; RV32IXQCI-LABEL: bare_select_float:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
%1 = select i1 %a, float %b, float %c
ret float %1
}
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index ec1f8aeddcaaf..02b562c130657 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
@@ -83,6 +85,44 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV32I-NEXT: .LBB0_28:
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: foo:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lw a5, 0(a1)
+; RV32IXQCI-NEXT: lw a2, 0(a1)
+; RV32IXQCI-NEXT: lw a4, 0(a1)
+; RV32IXQCI-NEXT: lw t5, 0(a1)
+; RV32IXQCI-NEXT: lw t4, 0(a1)
+; RV32IXQCI-NEXT: lw t2, 0(a1)
+; RV32IXQCI-NEXT: lw t1, 0(a1)
+; RV32IXQCI-NEXT: lw t0, 0(a1)
+; RV32IXQCI-NEXT: lw a7, 0(a1)
+; RV32IXQCI-NEXT: lw a6, 0(a1)
+; RV32IXQCI-NEXT: lw t3, 0(a1)
+; RV32IXQCI-NEXT: lw a3, 0(a1)
+; RV32IXQCI-NEXT: bltz t3, .LBB0_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: li t6, 0
+; RV32IXQCI-NEXT: qc.mveq a5, a0, a5, a0
+; RV32IXQCI-NEXT: qc.mvne a2, a5, a2, a5
+; RV32IXQCI-NEXT: qc.mvltu a4, a4, a2, a2
+; RV32IXQCI-NEXT: qc.mvgeu t5, a4, t5, a4
+; RV32IXQCI-NEXT: qc.mvltu t4, t5, t4, t5
+; RV32IXQCI-NEXT: qc.mvgeu t2, t2, t4, t4
+; RV32IXQCI-NEXT: qc.mvlt t1, t1, t2, t2
+; RV32IXQCI-NEXT: qc.mvge t0, t1, t0, t1
+; RV32IXQCI-NEXT: qc.mvlt a7, t0, a7, t0
+; RV32IXQCI-NEXT: qc.mvge a6, a6, a7, a7
+; RV32IXQCI-NEXT: mv a3, t3
+; RV32IXQCI-NEXT: qc.mvge a3, t6, t3, a6
+; RV32IXQCI-NEXT: .LBB0_2:
+; RV32IXQCI-NEXT: lw a2, 0(a1)
+; RV32IXQCI-NEXT: lw a0, 0(a1)
+; RV32IXQCI-NEXT: li a1, 1024
+; RV32IXQCI-NEXT: qc.mvlt a2, a1, a2, a3
+; RV32IXQCI-NEXT: li a1, 2046
+; RV32IXQCI-NEXT: qc.mvltu a0, a1, t3, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: foo:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a2, 0(a1)
@@ -291,6 +331,23 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: numsignbits:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32IXQCI-NEXT: beqz a1, .LBB1_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: addi sp, sp, -16
+; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: mv s0, a0
+; RV32IXQCI-NEXT: call bar
+; RV32IXQCI-NEXT: mv a0, s0
+; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: addi sp, sp, 16
+; RV32IXQCI-NEXT: .LBB1_2:
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: numsignbits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
@@ -355,6 +412,14 @@ define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sge_int16min:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a3, 1048560
+; RV32IXQCI-NEXT: addi a3, a3, -1
+; RV32IXQCI-NEXT: qc.mvlt a2, a3, a0, a1
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_sge_int16min:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1048560
@@ -399,6 +464,17 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sge_int32min:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slti a6, a0, 0
+; RV32IXQCI-NEXT: slti a0, a1, 0
+; RV32IXQCI-NEXT: xori a0, a0, 1
+; RV32IXQCI-NEXT: qc.selecteqi a1, -1, a6, a0
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a4
+; RV32IXQCI-NEXT: qc.selectnei a1, 0, a3, a5
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_sge_int32min:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 524288
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index 6275d1a7eb84b..a2a0a4e9177f6 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -7,6 +7,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32-XQCICM
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32-XQCICS
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
@@ -43,6 +45,12 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_trunc:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -94,6 +102,12 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_param:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -145,6 +159,12 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_eq:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB2_2
@@ -196,6 +216,12 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ne:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB3_2
@@ -247,6 +273,12 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ugt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB4_2
@@ -298,6 +330,12 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_uge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB5_2
@@ -349,6 +387,12 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ult:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB6_2
@@ -400,6 +444,12 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_ule:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB7_2
@@ -451,6 +501,12 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_sgt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB8_2
@@ -502,6 +558,12 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_sge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvge a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB9_2
@@ -553,6 +615,12 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_slt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB10_2
@@ -604,6 +672,12 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-NEXT: mv a0, a2
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i32_sle:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: qc.mvge a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i32_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB11_2
@@ -662,6 +736,14 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a4
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_trunc:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a1, a0, 1
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: qc.selectnei a1, 0, a3, a5
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a4
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -722,6 +804,15 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_param:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: andi a5, a0, 1
+; RV32IXQCI-NEXT: mv a0, a5
+; RV32IXQCI-NEXT: qc.selectnei a5, 0, a2, a4
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a3
+; RV32IXQCI-NEXT: mv a1, a5
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -788,6 +879,16 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_eq:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a1, a1, a3
+; RV32IXQCI-NEXT: xor a0, a0, a2
+; RV32IXQCI-NEXT: or a1, a1, a0
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB14_2
@@ -854,6 +955,16 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ne:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a1, a1, a3
+; RV32IXQCI-NEXT: xor a0, a0, a2
+; RV32IXQCI-NEXT: or a1, a1, a0
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB15_2
@@ -929,6 +1040,17 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ugt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: sltu a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB16_2
@@ -1004,6 +1126,17 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_uge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: sltu a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB17_2
@@ -1079,6 +1212,17 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ult:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: sltu a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB18_2
@@ -1154,6 +1298,17 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_ule:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: sltu a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB19_2
@@ -1229,6 +1384,17 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_sgt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: slt a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB20_2
@@ -1304,6 +1470,17 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_sge:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: slt a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB21_2
@@ -1379,6 +1556,17 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_slt:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a2
+; RV32IXQCI-NEXT: slt a2, a1, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB22_2
@@ -1454,6 +1642,17 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: ret
;
+; RV32IXQCI-LABEL: select_i64_sle:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a2, a0
+; RV32IXQCI-NEXT: slt a2, a3, a1
+; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_i64_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB23_2
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index bc56408c0ca0f..364594357a98b 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -5,6 +5,8 @@
; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+zicond -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32ZICOND %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
@@ -25,6 +27,10 @@ define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_easy:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_const_int_easy:
; RV64: # %bb.0:
; RV64-NEXT: ret
@@ -39,6 +45,12 @@ define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_one_away:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 4
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_const_int_one_away:
; RV64: # %bb.0:
; RV64-NEXT: li a1, 4
@@ -54,6 +66,11 @@ define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
; RV32-NEXT: slli a0, a0, 2
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_pow2_zero:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slli a0, a0, 2
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_const_int_pow2_zero:
; RV64: # %bb.0:
; RV64-NEXT: slli a0, a0, 2
@@ -90,6 +107,12 @@ define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
; RV32ZICOND-NEXT: addi a0, a0, 6
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_int_harder:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 38
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_const_int_harder:
; RV64I: # %bb.0:
; RV64I-NEXT: bnez a0, .LBB3_2
@@ -152,6 +175,13 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
; RV32ZICOND-NEXT: add a0, a0, a1
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_const_fp:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 264192
+; RV32IXQCI-NEXT: lui a2, 263168
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_const_fp:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0
@@ -194,6 +224,13 @@ define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwi
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_eq_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: snez a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_eq_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -213,6 +250,13 @@ define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwi
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ne_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: seqz a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ne_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -231,6 +275,12 @@ define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sgt_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a1, a0
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sgt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a1, a0
@@ -248,6 +298,12 @@ define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_slt_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_slt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a0, a1
@@ -265,6 +321,12 @@ define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sge_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sge_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a0, a1
@@ -282,6 +344,12 @@ define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sle_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a1, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sle_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a1, a0
@@ -299,6 +367,12 @@ define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ugt_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a1, a0
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ugt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a1, a0
@@ -316,6 +390,12 @@ define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ult_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a1
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ult_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a0, a1
@@ -333,6 +413,12 @@ define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_uge_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a0, a1
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_uge_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a0, a1
@@ -350,6 +436,12 @@ define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounw
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ule_zero_negone:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: sltu a0, a1, a0
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ule_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a1, a0
@@ -368,6 +460,13 @@ define i32 @select_eq_1_2(i32 signext %a, i32 signext %b) {
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_eq_1_2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: snez a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_eq_1_2:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -387,6 +486,13 @@ define i32 @select_ne_1_2(i32 signext %a, i32 signext %b) {
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ne_1_2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: seqz a0, a0
+; RV32IXQCI-NEXT: addi a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ne_1_2:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -408,6 +514,15 @@ define i32 @select_eq_10000_10001(i32 signext %a, i32 signext %b) {
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_eq_10000_10001:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 2
+; RV32IXQCI-NEXT: seqz a0, a0
+; RV32IXQCI-NEXT: addi a1, a1, 1810
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_eq_10000_10001:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -431,6 +546,15 @@ define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_ne_10001_10002:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 2
+; RV32IXQCI-NEXT: snez a0, a0
+; RV32IXQCI-NEXT: addi a1, a1, 1810
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_ne_10001_10002:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
@@ -452,6 +576,13 @@ define i32 @select_slt_zero_constant1_constant2(i32 signext %x) {
; RV32-NEXT: addi a0, a0, -3
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_slt_zero_constant1_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: andi a0, a0, 10
+; RV32IXQCI-NEXT: addi a0, a0, -3
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_slt_zero_constant1_constant2:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
@@ -471,6 +602,13 @@ define i32 @select_sgt_negative_one_constant1_constant2(i32 signext %x) {
; RV32-NEXT: addi a0, a0, 7
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: select_sgt_negative_one_constant1_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: andi a0, a0, -10
+; RV32IXQCI-NEXT: addi a0, a0, 7
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: select_sgt_negative_one_constant1_constant2:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index 2e1784d369680..c0b80cb70be81 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -4,6 +4,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s
; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i16 @select_xor_1(i16 %A, i8 %cond) {
; RV32IM-LABEL: select_xor_1:
diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll
index fb34123e7ad2a..8b976163351ae 100644
--- a/llvm/test/CodeGen/RISCV/xqcicli.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicli.ll
@@ -4,6 +4,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICLI
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq:
@@ -18,6 +20,11 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieq a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -37,6 +44,11 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.line a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -56,6 +68,11 @@ define i32 @select_cc_example_slt(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilt a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilt a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -75,6 +92,11 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lige a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lige a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -94,6 +116,11 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -113,6 +140,11 @@ define i32 @select_cc_example_ult(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, %x
%sel = select i1 %cmp, i32 11, i32 %a
@@ -132,6 +164,11 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.line a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -151,6 +188,11 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieq a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -170,6 +212,11 @@ define i32 @select_cc_example_slt_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lige a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lige a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -189,6 +236,11 @@ define i32 @select_cc_example_sge_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilt a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilt a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -208,6 +260,11 @@ define i32 @select_cc_example_uge_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -227,6 +284,11 @@ define i32 @select_cc_example_ult_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeu a0, a1, a2, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeu a0, a1, a2, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, %x
%sel = select i1 %cmp, i32 %a, i32 11
@@ -247,6 +309,11 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -267,6 +334,11 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -287,6 +359,11 @@ define i32 @select_cc_example_slti(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -307,6 +384,11 @@ define i32 @select_cc_example_sgei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -327,6 +409,11 @@ define i32 @select_cc_example_ulti(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -347,6 +434,11 @@ define i32 @select_cc_example_ugei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
%sel = select i1 %cmp, i32 11, i32 %a
@@ -367,6 +459,11 @@ define i32 @select_cc_example_eqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -387,6 +484,11 @@ define i32 @select_cc_example_nei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -407,6 +509,11 @@ define i32 @select_cc_example_slti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -427,6 +534,11 @@ define i32 @select_cc_example_sgei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -447,6 +559,11 @@ define i32 @select_cc_example_ulti_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -467,6 +584,11 @@ define i32 @select_cc_example_ugei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 12, %b
%sel = select i1 %cmp, i32 11, i32 %a
@@ -487,6 +609,11 @@ define i32 @select_cc_example_eqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -507,6 +634,11 @@ define i32 @select_cc_example_nei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -527,6 +659,11 @@ define i32 @select_cc_example_slti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -547,6 +684,11 @@ define i32 @select_cc_example_sgei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -567,6 +709,11 @@ define i32 @select_cc_example_ulti_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -587,6 +734,11 @@ define i32 @select_cc_example_ugei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 13, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 12, %b
%sel = select i1 %cmp, i32 %a, i32 11
@@ -607,6 +759,11 @@ define i32 @select_cc_example_eqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.linei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -627,6 +784,11 @@ define i32 @select_cc_example_nei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lieqi a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -647,6 +809,11 @@ define i32 @select_cc_example_slti_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligei a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slti_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligei a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -667,6 +834,11 @@ define i32 @select_cc_example_sgei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.lilti a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lilti a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -687,6 +859,11 @@ define i32 @select_cc_example_ulti_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.ligeui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ulti_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.ligeui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
@@ -707,6 +884,11 @@ define i32 @select_cc_example_ugei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICLI: # %bb.0: # %entry
; RV32IXQCICLI-NEXT: qc.liltui a0, a1, 12, 11
; RV32IXQCICLI-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.liltui a0, a1, 12, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %b, 12
%sel = select i1 %cmp, i32 %a, i32 11
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index beb2c6aff0053..a533fa9202333 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -4,6 +4,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32I-LABEL: select_example:
@@ -22,6 +24,12 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 0, a1
; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_example:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
%sel = select i1 %cond_trunc, i32 %x, i32 %y
@@ -44,6 +52,11 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -66,6 +79,11 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -88,6 +106,11 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -110,6 +133,11 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -132,6 +160,12 @@ define i32 @select_cc_example_slt(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -154,6 +188,12 @@ define i32 @select_cc_example_slt1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -176,6 +216,12 @@ define i32 @select_cc_example_sle(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sle:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -198,6 +244,12 @@ define i32 @select_cc_example_sle1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sle1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -220,6 +272,12 @@ define i32 @select_cc_example_sgt(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -242,6 +300,12 @@ define i32 @select_cc_example_sgt1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgt1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -264,6 +328,12 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -286,6 +356,12 @@ define i32 @select_cc_example_sge1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -308,6 +384,12 @@ define i32 @select_cc_example_ule(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -330,6 +412,12 @@ define i32 @select_cc_example_ule1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -352,6 +440,12 @@ define i32 @select_cc_example_ugt(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugt:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -374,6 +468,12 @@ define i32 @select_cc_example_ugt1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugt1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -396,6 +496,12 @@ define i32 @select_cc_example_ult(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -418,6 +524,12 @@ define i32 @select_cc_example_ult1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -440,6 +552,12 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -462,6 +580,12 @@ define i32 @select_cc_example_uge1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -483,6 +607,12 @@ define i32 @select_cc_example_eq_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mveq a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -504,6 +634,12 @@ define i32 @select_cc_example_ne_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvne a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -525,6 +661,12 @@ define i32 @select_cc_example_slt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlt a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_slt_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -546,6 +688,12 @@ define i32 @select_cc_example_sge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvge a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sge_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvge a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -567,6 +715,12 @@ define i32 @select_cc_example_sgt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvlt a3, a1, a0, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sgt_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvlt a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -588,6 +742,12 @@ define i32 @select_cc_example_sle_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvge a3, a1, a0, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_sle_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvge a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -609,6 +769,12 @@ define i32 @select_cc_example_ugt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltu a3, a1, a0, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ugt_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -630,6 +796,12 @@ define i32 @select_cc_example_ult_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ult_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -651,6 +823,12 @@ define i32 @select_cc_example_uge_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgeu a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_uge_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -672,6 +850,12 @@ define i32 @select_cc_example_ule_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvgeu a3, a1, a0, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule_reg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.mvgeu a3, a1, a0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -695,6 +879,13 @@ define i32 @select_cc_example_ule_neg(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICM-NEXT: qc.mvltu a3, a0, a1, a2
; RV32IXQCICM-NEXT: mv a0, a3
; RV32IXQCICM-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ule_neg:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: li a1, -10
+; RV32IXQCI-NEXT: qc.mvltu a3, a0, a1, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, -11
%sel = select i1 %cmp, i32 %x, i32 %y
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index 0e90b1fda0ea2..ae8eb2c997d9f 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -6,6 +6,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq_s1:
@@ -23,6 +25,12 @@ define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: andi a0, a0, 1
; RV32IXQCICS-NEXT: qc.selectinei a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_s1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a2, 12
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 %x, i32 12
@@ -46,6 +54,12 @@ define i32 @select_cc_example_eq_s2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: andi a0, a0, 1
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_s2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a2, 12
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 12, i32 %x
@@ -70,6 +84,13 @@ define i32 @select_cc_example_eq_s3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: li a1, 25
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a1, 12
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_s3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: li a1, 25
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 12
+; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 12, i32 25
@@ -91,6 +112,11 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -112,6 +138,11 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eq_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -133,6 +164,11 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -154,6 +190,11 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ne_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
@@ -174,6 +215,12 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 11
@@ -194,6 +241,12 @@ define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqi_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 11, i32 %x
@@ -214,6 +267,12 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 11
@@ -234,6 +293,12 @@ define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_nei_c:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 11, i32 %x
@@ -255,6 +320,12 @@ define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 12
%sel = select i1 %cmp, i32 %x, i32 11
@@ -276,6 +347,12 @@ define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %a
%sel = select i1 %cmp, i32 %x, i32 11
@@ -297,6 +374,12 @@ define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 12
%sel = select i1 %cmp, i32 11, i32 %x
@@ -318,6 +401,12 @@ define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_ieqi_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 12, %a
%sel = select i1 %cmp, i32 11, i32 %x
@@ -339,6 +428,12 @@ define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 12
%sel = select i1 %cmp, i32 %x, i32 11
@@ -360,6 +455,12 @@ define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei_c1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %a
%sel = select i1 %cmp, i32 %x, i32 11
@@ -381,6 +482,12 @@ define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei_c2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 12
%sel = select i1 %cmp, i32 11, i32 %x
@@ -402,6 +509,12 @@ define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_inei_c3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 12, %a
%sel = select i1 %cmp, i32 11, i32 %x
@@ -423,6 +536,11 @@ define i32 @select_cc_example_eqii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiieq a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_eqii:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectiieq a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 13, i32 11
@@ -444,6 +562,11 @@ define i32 @select_cc_example_neii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiine a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cc_example_neii:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: qc.selectiine a0, a1, 13, 11
+; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 13, i32 11
>From 994af6c37234ecdd4c1bd5761d25b749c5eb19e4 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 22:29:21 -0700
Subject: [PATCH 11/14] Add Comment
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 553120e3d9575..f3f98ae333028 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1579,7 +1579,7 @@ def : QCILICCIPatInv<SETGE, QC_LILTI, simm5>;
def : QCILICCIPatInv<SETLT, QC_LIGEI, simm5>;
def : QCILICCIPatInv<SETUGE, QC_LILTUI, uimm5>;
def : QCILICCIPatInv<SETULT, QC_LIGEUI, uimm5>;
-}
+} // Predicates = [HasVendorXqcicli, IsRV32]
let Predicates = [HasVendorXqcics, IsRV32] in {
// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
>From 0274afc1bf4242310dd05522c6765af30895e916 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 12 Aug 2025 23:48:37 -0700
Subject: [PATCH 12/14] Missed Test
---
llvm/test/CodeGen/RISCV/select.ll | 475 ++++++++++++++++++++++++++++++
1 file changed, 475 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index c0b80cb70be81..9933f3e1edba6 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -39,6 +39,14 @@ define i16 @select_xor_1(i16 %A, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a2, a1
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a1, a1, 31
+; RV32IXQCI-NEXT: srai a1, a1, 31
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -81,6 +89,14 @@ define i16 @select_xor_1b(i16 %A, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a2, a1
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_1b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a1, a1, 31
+; RV32IXQCI-NEXT: srai a1, a1, 31
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -119,6 +135,14 @@ define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -159,6 +183,14 @@ define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_2b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -199,6 +231,14 @@ define i16 @select_xor_3(i16 %A, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a2, a1
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a1, a1, 1
+; RV32IXQCI-NEXT: addi a1, a1, -1
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -241,6 +281,14 @@ define i16 @select_xor_3b(i16 %A, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a2, a1
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_3b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a1, a1, 1
+; RV32IXQCI-NEXT: addi a1, a1, -1
+; RV32IXQCI-NEXT: andi a1, a1, 43
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -279,6 +327,14 @@ define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_4:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -319,6 +375,14 @@ define i32 @select_xor_4b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: xor a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_xor_4b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -357,6 +421,14 @@ define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -397,6 +469,14 @@ define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -435,6 +515,14 @@ define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp eq i32 %and, 0
@@ -475,6 +563,14 @@ define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.eqz a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_1b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: slli a2, a2, 31
+; RV32IXQCI-NEXT: srai a2, a2, 31
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp ne i32 %and, 1
@@ -513,6 +609,14 @@ define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp eq i8 %and, 0
@@ -553,6 +657,14 @@ define i32 @select_or_2b(i32 %A, i32 %B, i8 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_2b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
%cmp10 = icmp ne i8 %and, 1
@@ -591,6 +703,14 @@ define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp eq i32 %and, 0
@@ -631,6 +751,14 @@ define i32 @select_or_3b(i32 %A, i32 %B, i32 %cond) {
; CHECKZICOND-NEXT: czero.nez a1, a1, a2
; CHECKZICOND-NEXT: or a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_or_3b:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: addi a2, a2, -1
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
%cmp10 = icmp ne i32 %and, 1
@@ -671,6 +799,13 @@ define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: addw a0, a2, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: and a0, a0, a1
+; RV32IXQCI-NEXT: add a0, a0, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -709,6 +844,13 @@ define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: addw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -750,6 +892,13 @@ define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: addw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_add_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: andi a0, a0, 42
+; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -798,6 +947,12 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_sub_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: sub a1, a1, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -836,6 +991,13 @@ define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: subw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_sub_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -877,6 +1039,13 @@ define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: subw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_sub_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: andi a0, a0, 42
+; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -915,6 +1084,12 @@ define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
; CHECKZICOND-NEXT: czero.nez a0, a2, a0
; CHECKZICOND-NEXT: or a0, a1, a0
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_and_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -953,6 +1128,12 @@ define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
; CHECKZICOND-NEXT: or a0, a2, a0
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_and_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: and a2, a2, a1
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -991,6 +1172,12 @@ define i32 @select_and_3(i1 zeroext %cond, i32 %a) {
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
; CHECKZICOND-NEXT: or a0, a2, a0
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_and_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: andi a2, a1, 42
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1039,6 +1226,33 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_udiv_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi sp, sp, -16
+; RV32IXQCI-NEXT: .cfi_def_cfa_offset 16
+; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: .cfi_offset ra, -4
+; RV32IXQCI-NEXT: .cfi_offset s0, -8
+; RV32IXQCI-NEXT: .cfi_offset s1, -12
+; RV32IXQCI-NEXT: mv s0, a2
+; RV32IXQCI-NEXT: mv s1, a0
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: call __udivsi3
+; RV32IXQCI-NEXT: qc.selectnei s1, 0, a0, s0
+; RV32IXQCI-NEXT: mv a0, s1
+; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: .cfi_restore ra
+; RV32IXQCI-NEXT: .cfi_restore s0
+; RV32IXQCI-NEXT: .cfi_restore s1
+; RV32IXQCI-NEXT: addi sp, sp, 16
+; RV32IXQCI-NEXT: .cfi_def_cfa_offset 0
+; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1087,6 +1301,33 @@ define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_udiv_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi sp, sp, -16
+; RV32IXQCI-NEXT: .cfi_def_cfa_offset 16
+; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: .cfi_offset ra, -4
+; RV32IXQCI-NEXT: .cfi_offset s0, -8
+; RV32IXQCI-NEXT: .cfi_offset s1, -12
+; RV32IXQCI-NEXT: mv s0, a1
+; RV32IXQCI-NEXT: mv s1, a0
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: call __udivsi3
+; RV32IXQCI-NEXT: qc.selectnei s1, 0, s0, a0
+; RV32IXQCI-NEXT: mv a0, s1
+; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: .cfi_restore ra
+; RV32IXQCI-NEXT: .cfi_restore s0
+; RV32IXQCI-NEXT: .cfi_restore s1
+; RV32IXQCI-NEXT: addi sp, sp, 16
+; RV32IXQCI-NEXT: .cfi_def_cfa_offset 0
+; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1155,6 +1396,33 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: or a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_udiv_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi sp, sp, -16
+; RV32IXQCI-NEXT: .cfi_def_cfa_offset 16
+; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IXQCI-NEXT: .cfi_offset ra, -4
+; RV32IXQCI-NEXT: .cfi_offset s0, -8
+; RV32IXQCI-NEXT: .cfi_offset s1, -12
+; RV32IXQCI-NEXT: mv s0, a1
+; RV32IXQCI-NEXT: mv s1, a0
+; RV32IXQCI-NEXT: li a1, 42
+; RV32IXQCI-NEXT: mv a0, s0
+; RV32IXQCI-NEXT: call __udivsi3
+; RV32IXQCI-NEXT: qc.selectnei s1, 0, s0, a0
+; RV32IXQCI-NEXT: mv a0, s1
+; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IXQCI-NEXT: .cfi_restore ra
+; RV32IXQCI-NEXT: .cfi_restore s0
+; RV32IXQCI-NEXT: .cfi_restore s1
+; RV32IXQCI-NEXT: addi sp, sp, 16
+; RV32IXQCI-NEXT: .cfi_def_cfa_offset 0
+; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1203,6 +1471,12 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_shl_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: sll a1, a1, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1241,6 +1515,13 @@ define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: sllw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_shl_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: sll a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1252,6 +1533,11 @@ define i32 @select_shl_3(i1 zeroext %cond, i32 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_shl_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1300,6 +1586,12 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_ashr_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: sra a1, a1, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1338,6 +1630,13 @@ define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: sraw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_ashr_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: sra a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1349,6 +1648,11 @@ define i32 @select_ashr_3(i1 zeroext %cond, i32 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_ashr_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1397,6 +1701,12 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_lshr_1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: srl a1, a1, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
%res = select i1 %cond, i32 %c, i32 %b
@@ -1435,6 +1745,13 @@ define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
; RV64IMZICOND-NEXT: srlw a0, a1, a0
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_lshr_2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: and a0, a0, a2
+; RV32IXQCI-NEXT: srl a0, a1, a0
+; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
%res = select i1 %cond, i32 %a, i32 %c
@@ -1446,6 +1763,11 @@ define i32 @select_lshr_3(i1 zeroext %cond, i32 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_lshr_3:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, 42
%res = select i1 %cond, i32 %a, i32 %c
@@ -1459,6 +1781,13 @@ define i32 @select_cst_not1(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: xori a0, a0, -6
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not1:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: xori a0, a0, -6
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 5, i32 -6
ret i32 %ret
@@ -1470,6 +1799,12 @@ define i32 @select_cst_not2(i32 signext %a) {
; CHECK-NEXT: srai a0, a0, 31
; CHECK-NEXT: xori a0, a0, -6
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, -6
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, 0
%ret = select i1 %cond, i32 5, i32 -6
ret i32 %ret
@@ -1481,6 +1816,12 @@ define i32 @select_cst_not3(i32 signext %a) {
; CHECK-NEXT: srai a0, a0, 31
; CHECK-NEXT: xori a0, a0, 5
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not3:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, 5
+; RV32IXQCI-NEXT: ret
%cond = icmp sgt i32 %a, -1
%ret = select i1 %cond, i32 5, i32 -6
ret i32 %ret
@@ -1529,6 +1870,14 @@ define i32 @select_cst_not4(i32 signext %a, i32 signext %b) {
; RV64IMZICOND-NEXT: addiw a1, a1, -1
; RV64IMZICOND-NEXT: xor a0, a0, a1
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 524288
+; RV32IXQCI-NEXT: addi a1, a1, -1
+; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 -2147483648, i32 2147483647
ret i32 %ret
@@ -1543,6 +1892,15 @@ define i32 @select_cst_not5(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: addi a1, a1, -5
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_not5:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: slt a0, a0, a1
+; RV32IXQCI-NEXT: lui a1, 16
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: addi a1, a1, -5
+; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 -65532, i32 65531
ret i32 %ret
@@ -1584,6 +1942,13 @@ define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 5
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_unknown:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a2, -7
+; RV32IXQCI-NEXT: qc.lilt a2, a0, a1, 5
+; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: ret
%cond = icmp slt i32 %a, %b
%ret = select i1 %cond, i32 5, i32 -7
ret i32 %ret
@@ -1623,6 +1988,12 @@ define i32 @select_cst1(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 10
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst1:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 20
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 10
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 10, i32 20
ret i32 %ret
}
@@ -1665,6 +2036,13 @@ define i32 @select_cst2(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 10
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 5
+; RV32IXQCI-NEXT: addi a1, a1, -480
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 10
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 10, i32 20000
ret i32 %ret
}
@@ -1713,6 +2091,15 @@ define i32 @select_cst3(i1 zeroext %cond) {
; CHECKZICOND-NEXT: addi a1, a1, 1328
; CHECKZICOND-NEXT: add a0, a0, a1
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst3:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 5
+; RV32IXQCI-NEXT: lui a2, 7
+; RV32IXQCI-NEXT: addi a1, a1, -480
+; RV32IXQCI-NEXT: addi a2, a2, 1328
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 30000, i32 20000
ret i32 %ret
}
@@ -1723,6 +2110,12 @@ define i32 @select_cst4(i1 zeroext %cond) {
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: xori a0, a0, 2047
; CHECK-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: neg a0, a0
+; RV32IXQCI-NEXT: xori a0, a0, 2047
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 -2048, i32 2047
ret i32 %ret
}
@@ -1763,6 +2156,14 @@ define i32 @select_cst5(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 2047
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst5:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 1
+; RV32IXQCI-NEXT: addi a1, a1, -2047
+; RV32IXQCI-NEXT: li a2, 2047
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2047, i32 2049
ret i32 %ret
}
@@ -1803,6 +2204,14 @@ define i32 @select_cst5_invert(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 2047
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst5_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: lui a1, 1
+; RV32IXQCI-NEXT: addi a1, a1, -2047
+; RV32IXQCI-NEXT: li a2, 2047
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2049, i32 2047
ret i32 %ret
}
@@ -1848,6 +2257,13 @@ define i32 @select_cst_diff2(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
; RV64IMZICOND-NEXT: addiw a0, a0, 120
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 122
+; RV32IXQCI-NEXT: li a2, 120
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 120, i32 122
ret i32 %ret
}
@@ -1886,6 +2302,13 @@ define i32 @select_cst_diff2_invert(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 122
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff2_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 120
+; RV32IXQCI-NEXT: li a2, 122
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 122, i32 120
ret i32 %ret
}
@@ -1924,6 +2347,12 @@ define i32 @select_cst_diff4(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 10
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff4:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 10
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 10, i32 6
ret i32 %ret
}
@@ -1962,6 +2391,12 @@ define i32 @select_cst_diff4_invert(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 6
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff4_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 6
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 10
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 6, i32 10
ret i32 %ret
}
@@ -2000,6 +2435,12 @@ define i32 @select_cst_diff8(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 14
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff8:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 14
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 14, i32 6
ret i32 %ret
}
@@ -2045,6 +2486,12 @@ define i32 @select_cst_diff8_invert(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
; RV64IMZICOND-NEXT: addiw a0, a0, 6
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff8_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 6
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 14
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 6, i32 14
ret i32 %ret
}
@@ -2084,6 +2531,12 @@ define i32 @select_cst_diff1024(i1 zeroext %cond) {
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
; CHECKZICOND-NEXT: addi a0, a0, 1030
; CHECKZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff1024:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 1030
+; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 1030, i32 6
ret i32 %ret
}
@@ -2129,6 +2582,12 @@ define i32 @select_cst_diff1024_invert(i1 zeroext %cond) {
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
; RV64IMZICOND-NEXT: addiw a0, a0, 6
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_cst_diff1024_invert:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a1, 1030
+; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 6
+; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 6, i32 1030
ret i32 %ret
}
@@ -2183,6 +2642,14 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
; RV64IMZICOND-NEXT: or a0, a2, a0
; RV64IMZICOND-NEXT: sd a0, 0(a1)
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_redundant_czero_eqz1:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a2, a0
+; RV32IXQCI-NEXT: sw a0, 0(a1)
+; RV32IXQCI-NEXT: ret
entry:
%3 = icmp eq ptr %0, null
%4 = select i1 %3, ptr @select_redundant_czero_eqz_data, ptr %0
@@ -2237,6 +2704,14 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
; RV64IMZICOND-NEXT: or a0, a0, a2
; RV64IMZICOND-NEXT: sd a0, 0(a1)
; RV64IMZICOND-NEXT: ret
+;
+; RV32IXQCI-LABEL: select_redundant_czero_eqz2:
+; RV32IXQCI: # %bb.0: # %entry
+; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a0, a2
+; RV32IXQCI-NEXT: sw a0, 0(a1)
+; RV32IXQCI-NEXT: ret
entry:
%3 = icmp ne ptr %0, null
%4 = select i1 %3, ptr %0, ptr @select_redundant_czero_eqz_data
>From a1cdd6d1609564d93ea52fa823a96a8d80f34b20 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Wed, 13 Aug 2025 00:02:14 -0700
Subject: [PATCH 13/14] More reasonable target features for test
---
llvm/test/CodeGen/RISCV/select.ll | 81 +++++--------------------------
1 file changed, 11 insertions(+), 70 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index 9933f3e1edba6..37eb0736aa304 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s
; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i16 @select_xor_1(i16 %A, i8 %cond) {
@@ -1229,29 +1229,8 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_udiv_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi sp, sp, -16
-; RV32IXQCI-NEXT: .cfi_def_cfa_offset 16
-; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: .cfi_offset ra, -4
-; RV32IXQCI-NEXT: .cfi_offset s0, -8
-; RV32IXQCI-NEXT: .cfi_offset s1, -12
-; RV32IXQCI-NEXT: mv s0, a2
-; RV32IXQCI-NEXT: mv s1, a0
-; RV32IXQCI-NEXT: mv a0, a1
-; RV32IXQCI-NEXT: mv a1, a2
-; RV32IXQCI-NEXT: call __udivsi3
-; RV32IXQCI-NEXT: qc.selectnei s1, 0, a0, s0
-; RV32IXQCI-NEXT: mv a0, s1
-; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: .cfi_restore ra
-; RV32IXQCI-NEXT: .cfi_restore s0
-; RV32IXQCI-NEXT: .cfi_restore s1
-; RV32IXQCI-NEXT: addi sp, sp, 16
-; RV32IXQCI-NEXT: .cfi_def_cfa_offset 0
+; RV32IXQCI-NEXT: divu a1, a1, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
@@ -1304,29 +1283,8 @@ define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_udiv_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi sp, sp, -16
-; RV32IXQCI-NEXT: .cfi_def_cfa_offset 16
-; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: .cfi_offset ra, -4
-; RV32IXQCI-NEXT: .cfi_offset s0, -8
-; RV32IXQCI-NEXT: .cfi_offset s1, -12
-; RV32IXQCI-NEXT: mv s0, a1
-; RV32IXQCI-NEXT: mv s1, a0
-; RV32IXQCI-NEXT: mv a0, a1
-; RV32IXQCI-NEXT: mv a1, a2
-; RV32IXQCI-NEXT: call __udivsi3
-; RV32IXQCI-NEXT: qc.selectnei s1, 0, s0, a0
-; RV32IXQCI-NEXT: mv a0, s1
-; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: .cfi_restore ra
-; RV32IXQCI-NEXT: .cfi_restore s0
-; RV32IXQCI-NEXT: .cfi_restore s1
-; RV32IXQCI-NEXT: addi sp, sp, 16
-; RV32IXQCI-NEXT: .cfi_def_cfa_offset 0
+; RV32IXQCI-NEXT: divu a2, a1, a2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
@@ -1399,29 +1357,12 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
;
; RV32IXQCI-LABEL: select_udiv_3:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi sp, sp, -16
-; RV32IXQCI-NEXT: .cfi_def_cfa_offset 16
-; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: .cfi_offset ra, -4
-; RV32IXQCI-NEXT: .cfi_offset s0, -8
-; RV32IXQCI-NEXT: .cfi_offset s1, -12
-; RV32IXQCI-NEXT: mv s0, a1
-; RV32IXQCI-NEXT: mv s1, a0
-; RV32IXQCI-NEXT: li a1, 42
-; RV32IXQCI-NEXT: mv a0, s0
-; RV32IXQCI-NEXT: call __udivsi3
-; RV32IXQCI-NEXT: qc.selectnei s1, 0, s0, a0
-; RV32IXQCI-NEXT: mv a0, s1
-; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IXQCI-NEXT: .cfi_restore ra
-; RV32IXQCI-NEXT: .cfi_restore s0
-; RV32IXQCI-NEXT: .cfi_restore s1
-; RV32IXQCI-NEXT: addi sp, sp, 16
-; RV32IXQCI-NEXT: .cfi_def_cfa_offset 0
+; RV32IXQCI-NEXT: srli a2, a1, 1
+; RV32IXQCI-NEXT: lui a3, 199729
+; RV32IXQCI-NEXT: addi a3, a3, -975
+; RV32IXQCI-NEXT: mulhu a2, a2, a3
+; RV32IXQCI-NEXT: srli a2, a2, 2
+; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, 42
>From 5c3b90b7c3a54a03fd5e167ee618d462c1e4d85f Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 2 Sep 2025 21:05:41 -0700
Subject: [PATCH 14/14] Prioritise Xqcicm over Xqcics
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 42 +++----
llvm/test/CodeGen/RISCV/select-bare.ll | 6 +-
llvm/test/CodeGen/RISCV/select-cc.ll | 20 +--
llvm/test/CodeGen/RISCV/select-cond.ll | 107 +++++++++--------
llvm/test/CodeGen/RISCV/select-const.ll | 109 ++++++++++++++++-
llvm/test/CodeGen/RISCV/select.ll | 67 +++++++----
llvm/test/CodeGen/RISCV/xqcicm.ll | 17 ++-
llvm/test/CodeGen/RISCV/xqcics.ll | 127 +++++++++++++++++++-
9 files changed, 375 insertions(+), 124 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f24a3ed86d2c9..8ce251e916d02 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1492,6 +1492,8 @@ def HasVendorXqcicm
: Predicate<"Subtarget->hasVendorXqcicm()">,
AssemblerPredicate<(all_of FeatureVendorXqcicm),
"'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
+def NoVendorXqcicm
+ : Predicate<"!Subtarget->hasVendorXqcicm()">;
def FeatureVendorXqcics
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
@@ -1499,8 +1501,6 @@ def HasVendorXqcics
: Predicate<"Subtarget->hasVendorXqcics()">,
AssemblerPredicate<(all_of FeatureVendorXqcics),
"'Xqcics' (Qualcomm uC Conditional Select Extension)">;
-def NoVendorXqcics
- : Predicate<"!Subtarget->hasVendorXqcics()">;
def FeatureVendorXqcicsr
: RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 9d2099109564a..b46f7dbe85259 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1525,6 +1525,13 @@ let Predicates = [HasVendorXqciint, IsRV32] in
def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
let Predicates = [HasVendorXqcicm, IsRV32] in {
+// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
+// This exists to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETNE, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
+ (QC_MVNEI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETEQ, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
+ (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
+
def : QCIMVCCPat<SETEQ, QC_MVEQ>;
def : QCIMVCCPat<SETNE, QC_MVNE>;
def : QCIMVCCPat<SETLT, QC_MVLT>;
@@ -1532,25 +1539,14 @@ def : QCIMVCCPat<SETULT, QC_MVLTU>;
def : QCIMVCCPat<SETGE, QC_MVGE>;
def : QCIMVCCPat<SETUGE, QC_MVGEU>;
+def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5>;
+def : QCIMVCCIPat<SETNE, QC_MVNEI, simm5>;
def : QCIMVCCIPat<SETLT, QC_MVLTI, simm5>;
def : QCIMVCCIPat<SETULT, QC_MVLTUI, uimm5>;
def : QCIMVCCIPat<SETGE, QC_MVGEI, simm5>;
def : QCIMVCCIPat<SETUGE, QC_MVGEUI, uimm5>;
}
-// Prioritize Xqcics over these patterns.
-let Predicates = [HasVendorXqcicm, NoVendorXqcics, IsRV32] in {
-// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
-// This exists to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
-def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETNE, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
- (QC_MVNEI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
-def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rs1), (i32 0), SETEQ, (i32 GPRNoX0:$rs3), (i32 GPRNoX0:$rd))),
- (QC_MVEQI GPRNoX0:$rd, GPRNoX0:$rs1, 0, GPRNoX0:$rs3)>;
-
-def : QCIMVCCIPat<SETEQ, QC_MVEQI, simm5>;
-def : QCIMVCCIPat<SETNE, QC_MVNEI, simm5>;
-}
-
let Predicates = [HasVendorXqcicli, IsRV32] in {
def : QCILICCPat<SETEQ, QC_LIEQ>;
def : QCILICCPat<SETNE, QC_LINE>;
@@ -1584,20 +1580,11 @@ def : QCILICCIPatInv<SETULT, QC_LIGEUI, uimm5>;
let Predicates = [HasVendorXqcics, IsRV32] in {
// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
// These exist to prioritise over the `Select_GPR_Using_CC_GPR` pattern.
-
-def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
- (QC_SELECTNEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
-def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETEQ, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
- (QC_SELECTEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
-
def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), simm5:$simm2)),
(QC_SELECTINEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, simm5:$simm2, (i32 GPRNoX0:$rs2))),
(QC_SELECTIEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, simm5:$simm2)>;
-def : QCISELECTCCIPat<SETEQ, QC_SELECTEQI>;
-def : QCISELECTCCIPat<SETNE, QC_SELECTNEI>;
-
def : QCISELECTICCIPat<SETEQ, QC_SELECTIEQI>;
def : QCISELECTICCIPat<SETNE, QC_SELECTINEI>;
@@ -1614,6 +1601,17 @@ def : QCISELECTIICCPat<SETEQ, QC_SELECTIIEQ>;
def : QCISELECTIICCPat<SETNE, QC_SELECTIINE>;
} // Predicates = [HasVendorXqcics, IsRV32]
+// Prioritize Xqcicm over these patterns, because Xqcicm is compressible.
+let Predicates = [HasVendorXqcics, NoVendorXqcicm, IsRV32] in {
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETNE, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
+ (QC_SELECTNEI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+def : Pat<(i32 (riscv_selectcc (i32 GPRNoX0:$rd), (i32 0), SETEQ, (i32 GPRNoX0:$rs2), (i32 GPRNoX0:$rs3))),
+ (QC_SELECTEQI GPRNoX0:$rd, (i32 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+
+def : QCISELECTCCIPat<SETEQ, QC_SELECTEQI>;
+def : QCISELECTCCIPat<SETNE, QC_SELECTNEI>;
+}
+
let Predicates = [HasVendorXqcilsm, IsRV32] in {
def : Pat<(qc_setwmi GPR:$rs3, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7),
(QC_SETWMI GPR:$rs3, GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb00:$uimm7)>;
diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll
index e6b742375df57..796121ac572ce 100644
--- a/llvm/test/CodeGen/RISCV/select-bare.ll
+++ b/llvm/test/CodeGen/RISCV/select-bare.ll
@@ -26,7 +26,8 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32IXQCI-LABEL: bare_select:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
@@ -52,7 +53,8 @@ define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32IXQCI-LABEL: bare_select_float:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
%1 = select i1 %a, float %b, float %c
ret float %1
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index 4fbb8761b110c..14055dff40d42 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -333,19 +333,20 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
;
; RV32IXQCI-LABEL: numsignbits:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a3, a2
-; RV32IXQCI-NEXT: beqz a1, .LBB1_2
-; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: addi sp, sp, -16
; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCI-NEXT: mv s0, a0
+; RV32IXQCI-NEXT: mv s0, a2
+; RV32IXQCI-NEXT: qc.mveqi s0, a0, 0, a3
+; RV32IXQCI-NEXT: beqz a1, .LBB1_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: mv a0, s0
; RV32IXQCI-NEXT: call bar
+; RV32IXQCI-NEXT: .LBB1_2:
; RV32IXQCI-NEXT: mv a0, s0
; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IXQCI-NEXT: addi sp, sp, 16
-; RV32IXQCI-NEXT: .LBB1_2:
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: numsignbits:
@@ -469,10 +470,11 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
; RV32IXQCI-NEXT: srli a6, a0, 31
; RV32IXQCI-NEXT: srli a0, a1, 31
; RV32IXQCI-NEXT: xori a0, a0, 1
-; RV32IXQCI-NEXT: qc.selecteqi a1, -1, a6, a0
-; RV32IXQCI-NEXT: mv a0, a1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a4
-; RV32IXQCI-NEXT: qc.selectnei a1, 0, a3, a5
+; RV32IXQCI-NEXT: qc.mveqi a0, a1, -1, a6
+; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32IXQCI-NEXT: qc.mvnei a5, a0, 0, a3
+; RV32IXQCI-NEXT: mv a0, a4
+; RV32IXQCI-NEXT: mv a1, a5
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_sge_int32min:
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index a2a0a4e9177f6..b88fe9aae18ec 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -48,7 +48,8 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32IXQCI-LABEL: select_i32_trunc:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_trunc:
@@ -105,7 +106,8 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32IXQCI-LABEL: select_i32_param:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i32_param:
@@ -738,10 +740,11 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
;
; RV32IXQCI-LABEL: select_i64_trunc:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: andi a1, a0, 1
-; RV32IXQCI-NEXT: mv a0, a1
-; RV32IXQCI-NEXT: qc.selectnei a1, 0, a3, a5
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a4
+; RV32IXQCI-NEXT: mv a1, a5
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a3
+; RV32IXQCI-NEXT: mv a0, a4
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_trunc:
@@ -806,11 +809,11 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
;
; RV32IXQCI-LABEL: select_i64_param:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: andi a5, a0, 1
-; RV32IXQCI-NEXT: mv a0, a5
-; RV32IXQCI-NEXT: qc.selectnei a5, 0, a2, a4
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a3
-; RV32IXQCI-NEXT: mv a1, a5
+; RV32IXQCI-NEXT: andi a0, a0, 1
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 0, a1
+; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: mv a1, a4
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_param:
@@ -883,10 +886,11 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a1, a1, a3
; RV32IXQCI-NEXT: xor a0, a0, a2
-; RV32IXQCI-NEXT: or a1, a1, a0
-; RV32IXQCI-NEXT: mv a0, a1
-; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: qc.mveqi a6, a0, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a0, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_eq:
@@ -959,10 +963,11 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a1, a1, a3
; RV32IXQCI-NEXT: xor a0, a0, a2
-; RV32IXQCI-NEXT: or a1, a1, a0
-; RV32IXQCI-NEXT: mv a0, a1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: qc.mvnei a6, a0, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a0, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ne:
@@ -1045,10 +1050,10 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: sltu a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ugt:
@@ -1131,10 +1136,10 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: sltu a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_uge:
@@ -1217,10 +1222,10 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: sltu a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ult:
@@ -1303,10 +1308,10 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: sltu a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_ule:
@@ -1389,10 +1394,10 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: slt a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_sgt:
@@ -1475,10 +1480,10 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: slt a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_sge:
@@ -1561,10 +1566,10 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a0, a2
; RV32IXQCI-NEXT: slt a2, a1, a3
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selectnei a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mvnei a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_slt:
@@ -1647,10 +1652,10 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32IXQCI-NEXT: sltu a0, a2, a0
; RV32IXQCI-NEXT: slt a2, a3, a1
; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a0
-; RV32IXQCI-NEXT: mv a0, a2
-; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32IXQCI-NEXT: qc.selecteqi a2, 0, a5, a7
-; RV32IXQCI-NEXT: mv a1, a2
+; RV32IXQCI-NEXT: qc.mveqi a6, a2, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a7, a2, 0, a5
+; RV32IXQCI-NEXT: mv a0, a6
+; RV32IXQCI-NEXT: mv a1, a7
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_i64_sle:
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 98520b964733a..1fac05f6e451c 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -177,9 +177,10 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
;
; RV32IXQCI-LABEL: select_const_fp:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: lui a1, 264192
; RV32IXQCI-NEXT: lui a2, 263168
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: lui a1, 264192
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_const_fp:
@@ -650,6 +651,16 @@ define i32 @select_nonnegative_lui_addi(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_nonnegative_lui_addi:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: mv a1, a0
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: bgez a1, .LBB21_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: .LBB21_2:
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_nonnegative_lui_addi:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0
@@ -713,6 +724,16 @@ define i32 @select_nonnegative_lui_addi_swapped(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: select_nonnegative_lui_addi_swapped:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB22_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB22_2:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: select_nonnegative_lui_addi_swapped:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB22_2
@@ -778,6 +799,17 @@ define i32 @diff_shl_addi(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: diff_shl_addi:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB23_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: addi a0, a0, 25
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB23_2:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: diff_shl_addi:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB23_2
@@ -842,6 +874,17 @@ define i32 @diff_shl_addi2(i32 signext %x) {
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: diff_shl_addi2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB24_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: li a0, 25
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB24_2:
+; RV32IXQCI-NEXT: lui a0, 4
+; RV32IXQCI-NEXT: addi a0, a0, 25
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: diff_shl_addi2:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB24_2
@@ -884,6 +927,13 @@ define i32 @diff_pow2_24_16(i32 signext %x) {
; RV32-NEXT: addi a0, a0, 24
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: diff_pow2_24_16:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srai a0, a0, 31
+; RV32IXQCI-NEXT: andi a0, a0, -8
+; RV32IXQCI-NEXT: addi a0, a0, 24
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: diff_pow2_24_16:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
@@ -903,6 +953,13 @@ define i32 @diff_pow2_16_24(i32 signext %x) {
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: ret
;
+; RV32IXQCI-LABEL: diff_pow2_16_24:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: srli a0, a0, 28
+; RV32IXQCI-NEXT: andi a0, a0, 8
+; RV32IXQCI-NEXT: addi a0, a0, 16
+; RV32IXQCI-NEXT: ret
+;
; RV64-LABEL: diff_pow2_16_24:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 60
@@ -949,6 +1006,18 @@ define i32 @zext_or_constant(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: zext_or_constant:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB27_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB27_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: zext_or_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB27_2
@@ -1024,6 +1093,18 @@ define i32 @zext_or_constant2(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: zext_or_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bltz a0, .LBB28_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB28_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: xori a0, a0, 1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: zext_or_constant2:
; RV64I: # %bb.0:
; RV64I-NEXT: bltz a0, .LBB28_2
@@ -1100,6 +1181,18 @@ define i32 @sext_or_constant(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: sext_or_constant:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bgez a0, .LBB29_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB29_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: sext_or_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB29_2
@@ -1176,6 +1269,18 @@ define i32 @sext_or_constant2(i32 signext %x) {
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: ret
;
+; RV32IXQCI-LABEL: sext_or_constant2:
+; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: bltz a0, .LBB30_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: lui a0, 140
+; RV32IXQCI-NEXT: addi a0, a0, 417
+; RV32IXQCI-NEXT: ret
+; RV32IXQCI-NEXT: .LBB30_2:
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: addi a0, a0, -1
+; RV32IXQCI-NEXT: ret
+;
; RV64I-LABEL: sext_or_constant2:
; RV64I: # %bb.0:
; RV64I-NEXT: bltz a0, .LBB30_2
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index 6c0773522b870..9eb4e8096b621 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -951,7 +951,8 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_sub_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: sub a1, a1, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
@@ -1088,7 +1089,8 @@ define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_and_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: and a1, a1, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
@@ -1132,7 +1134,8 @@ define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_and_2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: and a2, a2, a1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
@@ -1176,7 +1179,8 @@ define i32 @select_and_3(i1 zeroext %cond, i32 %a) {
; RV32IXQCI-LABEL: select_and_3:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a2, a1, 42
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, 42
@@ -1230,7 +1234,8 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_udiv_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: divu a1, a1, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
@@ -1284,7 +1289,8 @@ define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_udiv_2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: divu a2, a1, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, %b
@@ -1362,7 +1368,8 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
; RV32IXQCI-NEXT: addi a3, a3, -975
; RV32IXQCI-NEXT: mulhu a2, a2, a3
; RV32IXQCI-NEXT: srli a2, a2, 2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, 42
@@ -1416,7 +1423,8 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_shl_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: sll a1, a1, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
@@ -1531,7 +1539,8 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_ashr_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: sra a1, a1, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
@@ -1646,7 +1655,8 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {
; RV32IXQCI-LABEL: select_lshr_1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: srl a1, a1, a2
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
@@ -2035,11 +2045,12 @@ define i32 @select_cst3(i1 zeroext %cond) {
;
; RV32IXQCI-LABEL: select_cst3:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: lui a1, 5
-; RV32IXQCI-NEXT: lui a2, 7
-; RV32IXQCI-NEXT: addi a1, a1, -480
-; RV32IXQCI-NEXT: addi a2, a2, 1328
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: lui a1, 7
+; RV32IXQCI-NEXT: lui a2, 5
+; RV32IXQCI-NEXT: addi a3, a1, 1328
+; RV32IXQCI-NEXT: addi a1, a2, -480
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a3
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 30000, i32 20000
ret i32 %ret
@@ -2103,7 +2114,8 @@ define i32 @select_cst5(i1 zeroext %cond) {
; RV32IXQCI-NEXT: lui a1, 1
; RV32IXQCI-NEXT: addi a1, a1, -2047
; RV32IXQCI-NEXT: li a2, 2047
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2047, i32 2049
ret i32 %ret
@@ -2147,9 +2159,10 @@ define i32 @select_cst5_invert(i1 zeroext %cond) {
; RV32IXQCI-LABEL: select_cst5_invert:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: lui a1, 1
-; RV32IXQCI-NEXT: addi a1, a1, -2047
-; RV32IXQCI-NEXT: li a2, 2047
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: addi a2, a1, -2047
+; RV32IXQCI-NEXT: li a1, 2047
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2049, i32 2047
ret i32 %ret
@@ -2199,9 +2212,10 @@ define i32 @select_cst_diff2(i1 zeroext %cond) {
;
; RV32IXQCI-LABEL: select_cst_diff2:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: li a1, 122
; RV32IXQCI-NEXT: li a2, 120
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: li a1, 122
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 120, i32 122
ret i32 %ret
@@ -2248,9 +2262,10 @@ define i32 @select_cst_diff2_invert(i1 zeroext %cond) {
;
; RV32IXQCI-LABEL: select_cst_diff2_invert:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: li a1, 120
; RV32IXQCI-NEXT: li a2, 122
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a2, a1
+; RV32IXQCI-NEXT: li a1, 120
+; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 122, i32 120
ret i32 %ret
@@ -2596,7 +2611,7 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
-; RV32IXQCI-NEXT: qc.selecteqi a0, 0, a2, a0
+; RV32IXQCI-NEXT: qc.mveqi a0, a0, 0, a2
; RV32IXQCI-NEXT: sw a0, 0(a1)
; RV32IXQCI-NEXT: ret
entry:
@@ -2658,8 +2673,8 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a0, a2
-; RV32IXQCI-NEXT: sw a0, 0(a1)
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a0
+; RV32IXQCI-NEXT: sw a2, 0(a1)
; RV32IXQCI-NEXT: ret
entry:
%3 = icmp ne ptr %0, null
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index a533fa9202333..1741be742323d 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -4,6 +4,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
@@ -28,7 +30,8 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32IXQCI-LABEL: select_example:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.selectnei a0, 0, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
@@ -55,7 +58,8 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCI-LABEL: select_cc_example_eq:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
@@ -82,7 +86,8 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCI-LABEL: select_cc_example_eq1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
@@ -109,7 +114,8 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCI-LABEL: select_cc_example_ne:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
@@ -136,7 +142,8 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCI-LABEL: select_cc_example_ne1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index ae8eb2c997d9f..38de8fbd78b36 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -5,7 +5,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
@@ -26,6 +26,12 @@ define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectinei a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eq_s1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: andi a0, a0, 1
+; RV32IXQCICM-NEXT: qc.selectinei a0, 0, a2, 12
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eq_s1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a0, a0, 1
@@ -55,6 +61,12 @@ define i32 @select_cc_example_eq_s2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eq_s2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: andi a0, a0, 1
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 0, a2, 12
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eq_s2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a0, a0, 1
@@ -85,6 +97,13 @@ define i32 @select_cc_example_eq_s3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a1, 12
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eq_s3:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: andi a0, a0, 1
+; RV32IXQCICM-NEXT: li a1, 25
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 0, a1, 12
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eq_s3:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a0, a0, 1
@@ -113,9 +132,16 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eq:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eq:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
@@ -139,9 +165,16 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eq_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eq_c:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
@@ -165,9 +198,16 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_ne:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_ne:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
@@ -191,9 +231,16 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_ne_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_ne_c:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
+; RV32IXQCI-NEXT: mv a0, a3
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
@@ -216,6 +263,11 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eqi:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieq a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eqi:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
@@ -242,6 +294,11 @@ define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eqi_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectine a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eqi_c:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
@@ -268,6 +325,11 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_nei:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectine a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_nei:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
@@ -294,6 +356,11 @@ define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_nei_c:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieq a0, a1, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_nei_c:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
@@ -321,6 +388,11 @@ define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_ieqi:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
@@ -348,6 +420,11 @@ define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi_c1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_ieqi_c1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
@@ -375,6 +452,11 @@ define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi_c2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_ieqi_c2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
@@ -402,6 +484,11 @@ define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_ieqi_c3:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_ieqi_c3:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
@@ -429,6 +516,11 @@ define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_inei:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_inei:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
@@ -456,6 +548,11 @@ define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_inei_c1:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_inei_c1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
@@ -483,6 +580,11 @@ define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_inei_c2:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_inei_c2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
@@ -510,6 +612,11 @@ define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_inei_c3:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_inei_c3:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
@@ -537,6 +644,11 @@ define i32 @select_cc_example_eqii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectiieq a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_eqii:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectiieq a0, a1, 13, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_eqii:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.selectiieq a0, a1, 13, 11
@@ -563,6 +675,11 @@ define i32 @select_cc_example_neii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32IXQCICS-NEXT: qc.selectiine a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
;
+; RV32IXQCICM-LABEL: select_cc_example_neii:
+; RV32IXQCICM: # %bb.0: # %entry
+; RV32IXQCICM-NEXT: qc.selectiine a0, a1, 13, 11
+; RV32IXQCICM-NEXT: ret
+;
; RV32IXQCI-LABEL: select_cc_example_neii:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.selectiine a0, a1, 13, 11
More information about the llvm-commits
mailing list