[llvm] [AMDGPU] Add shuffle optimizer pass (PR #155824)

[Matt Arsenault via llvm-commits]

================
@@ -3665,6 +3661,30 @@ def int_amdgcn_permlane32_swap :
             [IntrNoMem, IntrConvergent, IntrWillReturn,
              ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, IntrNoCallback, IntrNoFree]>;
 
+//===----------------------------------------------------------------------===//
+// Generic shuffle intrinsics (for CUDA/HIP and SPIR-V compatibility)
+//===----------------------------------------------------------------------===//
+
+def int_amdgcn_generic_shuffle :
+  Intrinsic<[llvm_any_ty],
+            [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
+            [IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
+
+def int_amdgcn_generic_shuffle_up :
+  Intrinsic<[llvm_any_ty],
+            [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
+            [IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
+
+def int_amdgcn_generic_shuffle_down :
+  Intrinsic<[llvm_any_ty],
+            [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
+            [IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
+
+def int_amdgcn_generic_shuffle_xor :
+  Intrinsic<[llvm_any_ty],
+            [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
+            [IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
----------------
arsenm wrote:

In general target intrinsics should not be trying to provide high level semantics. Can you instead start at the most universal target intrinsic usage and rewrite into one of the subtarget dependent forms?


This patch also doesn't have codegen for these intrinsics. You can't rely on an optimization pass folding them away 

https://github.com/llvm/llvm-project/pull/155824