[llvm] [RISCV] Added ROLW/RORW/SLLW/SRAW/SRLW for canCreateUndefOrPoisonForTargetNode (PR #152609)

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 27 04:53:57 PDT 2025


https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/152609

>From efa71acb85bf691535befdfd18b5ea3171b918d1 Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Wed, 6 Aug 2025 13:51:53 -0700
Subject: [PATCH] Added  ROLW/RORW + SLLW/SRAW/SRLW for
 canCreateUndefOrPoisonForTargetNode

Co-authored-by: RKSimon <RKSimon at users.noreply.github.com>
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index adbfbeb4669e7..d86ec003459d3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21477,6 +21477,14 @@ bool RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(
 
   // TODO: Add more target nodes.
   switch (Op.getOpcode()) {
+  case RISCVISD::SLLW:
+  case RISCVISD::SRAW:
+  case RISCVISD::SRLW:
+  case RISCVISD::RORW:
+  case RISCVISD::ROLW:
+    // Only the lower 5 bits of RHS are read, guaranteeing the rotate/shift
+    // amount is bounds.
+    return false;
   case RISCVISD::SELECT_CC:
     // Integer select_cc cannot create poison.
     // TODO: What are the FP poison semantics?



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