[llvm] [RISCV] Loosen the requirement of shadow stack codegen to Zimop (PR #152251)

[Ming-Yi Lai via llvm-commits]

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@@ -124,7 +124,10 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
   if (HasHWShadowStack) {
-    BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+    if (STI.hasStdExtZcmop())
+      BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoMOP_C_SSPUSH)).addReg(RAReg);
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mylai-mtk wrote:

C.SSPUSH does not take non-X1 registers, so I think at here it's better to drop the `addReg()` and instead `static_assert(RAReg == RISCV::X1)` so misuses could be found at compile time.

https://github.com/llvm/llvm-project/pull/152251