[llvm] [RISCV] Loosen the requirement of shadow stack codegen to Zimop (PR #152251)

[Jesse Huang via llvm-commits]

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@@ -62,6 +62,26 @@ defm SSAMOSWAP_W  : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
 let Predicates = [HasStdExtZicfiss, IsRV64] in
 defm SSAMOSWAP_D  : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
 
+let Predicates = [HasStdExtZimop] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in
+def PseudoMOP_SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
+                     "mop.rr.7", "$rs2"> {
+  let rd = 0b00000;
+  let rs1 = 0b00000;
+}
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1 in
+def PseudoMOP_SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "mop.r.28",
+                       "$rs1"> {
+  let rd = 0;
+  let imm12 = 0b110011011100;
+}
+}
+
+let Predicates = [HasStdExtZcmop] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in
+def PseudoMOP_C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.mop.1">;
+}
+
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jaidTw wrote:

I was attempting to achieve the compression of `sspush` -> `c.sspush` in the pipeline, and that way we would need to carry the encodings in the instructions because there's no mapping between `mop` and `c.mop` and that is why I didn't go with the `PseudoInstExpansion`.
However, I found it seems to be simpler to just determine whether we should compress or not at the emission time. So yeah, why not just changed it back to use `PseudoInstExpansion`.
I also agree your opinon on the disassembler behavior, I've updated the test accordingly.

https://github.com/llvm/llvm-project/pull/152251