[llvm] X86: Remove LOW32_ADDR_ACCESS_RBPRegClass (PR #155127)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/155127

This essentially reverts 86098ab10b3180a09762266d1f3046eb6f336137.

This was introduced for "ABIs like NaCl". Nacl support was recently
removed in 0d2e11f3e834e0c1803a6e00da35525b0d476eb2. Based on the
X86FrameLowering changes there, Is64Bit && TFI->Uses64BitFramePtr
are not reachable conditions.

>From 1e471a1a293fa1249b267821f2efbb69c9feeb93 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 24 Aug 2025 09:50:56 +0900
Subject: [PATCH] X86: Remove LOW32_ADDR_ACCESS_RBPRegClass

This essentially reverts 86098ab10b3180a09762266d1f3046eb6f336137.

This was introduced for "ABIs like NaCl". Nacl support was recently
removed in 0d2e11f3e834e0c1803a6e00da35525b0d476eb2. Based on the
X86FrameLowering changes there, Is64Bit && TFI->Uses64BitFramePtr
are not reachable conditions.
---
 llvm/lib/Target/X86/X86ISelLowering.cpp |  3 +--
 llvm/lib/Target/X86/X86RegisterInfo.cpp | 10 +---------
 llvm/lib/Target/X86/X86RegisterInfo.td  |  7 -------
 3 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 19131fbd4102b..2a35580e43a7b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61512,8 +61512,7 @@ static bool isGRClass(const TargetRegisterClass &RC) {
   return RC.hasSuperClassEq(&X86::GR8RegClass) ||
          RC.hasSuperClassEq(&X86::GR16RegClass) ||
          RC.hasSuperClassEq(&X86::GR32RegClass) ||
-         RC.hasSuperClassEq(&X86::GR64RegClass) ||
-         RC.hasSuperClassEq(&X86::LOW32_ADDR_ACCESS_RBPRegClass);
+         RC.hasSuperClassEq(&X86::GR64RegClass);
 }
 
 /// Check if \p RC is a vector register class.
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 595ad3290eedb..b79e508df7c97 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -204,15 +204,7 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
     // we can still use 64-bit register as long as we know the high bits
     // are zeros.
     // Reflect that in the returned register class.
-    if (Is64Bit) {
-      // When the target also allows 64-bit frame pointer and we do have a
-      // frame, this is fine to use it for the address accesses as well.
-      const X86FrameLowering *TFI = getFrameLowering(MF);
-      return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
-                 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
-                 : &X86::LOW32_ADDR_ACCESSRegClass;
-    }
-    return &X86::GR32RegClass;
+    return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
     if (Subtarget.isTarget64BitLP64())
       return &X86::GR64_NOSPRegClass;
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index e9ca25d808a56..1c58b31700b75 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -716,13 +716,6 @@ def GR64_NOREX2_NOSP : RegisterClass<"X86", [i64], 64,
 // which we do not have right now.
 def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;
 
-// When RBP is used as a base pointer in a 32-bit addresses environment,
-// this is also safe to use the full register to access addresses.
-// Since RBP will never be spilled, stick to a 32 alignment to save
-// on memory consumption.
-def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
-                                          (add LOW32_ADDR_ACCESS, RBP)>;
-
 // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;