[llvm] [AArch64] Copy CSNEG, CSINV, and CSINC computeKnownBitsForTargetNode from ARM (PR #155122)

via llvm-commits llvm-commits at lists.llvm.org
Sat Aug 23 14:48:59 PDT 2025


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.cpp
``````````

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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d6bba9909..cfac137f3 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -19984,7 +19984,7 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     break;
   case ARMISD::CMOV: {
     // Bits are known zero/one if known on the LHS and RHS.
-    Known = DAG.computeKnownBits(Op.getOperand(0), Depth+1);
+    Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
     KnownBits KnownRHS = DAG.computeKnownBits(Op.getOperand(1), Depth+1);
     Known = Known.intersectWith(KnownRHS);
     return;

``````````

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https://github.com/llvm/llvm-project/pull/155122


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