[llvm] [RISCV] Mark More Relocs as Relaxable (PR #151422)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 23 12:16:36 PDT 2025
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/151422
>From a41bb0608aa39118cc90f3fc7421ad51b9166d15 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Wed, 30 Jul 2025 16:32:05 -0700
Subject: [PATCH 1/7] [RISCV] Mark More Relocs as Relaxable
Since this code was last reviewed, more relaxations have been added for
existing standard relocations that LLVM didn't have marked as relaxable.
This code ensures that LLVM marks the following relocations (and their
respective fixups) as relaxable:
- `R_RISCV_JAL`
- `R_RISCV_GOT_HI20`
- `R_RISCV_TPREL_HI20`
- `R_RISCV_TLSDESC_HI20`
---
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 9 +-
llvm/test/MC/RISCV/linker-relaxation.s | 112 +++++++++++-------
2 files changed, 78 insertions(+), 43 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index cbeabdddb9371..c7135c8e7ab7f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -628,9 +628,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
RelaxCandidate = true;
break;
- case ELF::R_RISCV_TPREL_HI20:
- RelaxCandidate = true;
- break;
case ELF::R_RISCV_CALL_PLT:
FixupKind = RISCV::fixup_riscv_call_plt;
RelaxCandidate = true;
@@ -639,11 +636,17 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
RelaxCandidate = true;
break;
+ case ELF::R_RISCV_GOT_HI20:
+ case ELF::R_RISCV_TPREL_HI20:
+ case ELF::R_RISCV_TLSDESC_HI20:
+ RelaxCandidate = true;
+ break;
}
} else if (Kind == MCExpr::SymbolRef || Kind == MCExpr::Binary) {
// FIXME: Sub kind binary exprs have chance of underflow.
if (MIFrm == RISCVII::InstFormatJ) {
FixupKind = RISCV::fixup_riscv_jal;
+ RelaxCandidate = true;
} else if (MIFrm == RISCVII::InstFormatB) {
FixupKind = RISCV::fixup_riscv_branch;
} else if (MIFrm == RISCVII::InstFormatCJ) {
diff --git a/llvm/test/MC/RISCV/linker-relaxation.s b/llvm/test/MC/RISCV/linker-relaxation.s
index 6b0685baaa69e..c5c4e4877ff2e 100644
--- a/llvm/test/MC/RISCV/linker-relaxation.s
+++ b/llvm/test/MC/RISCV/linker-relaxation.s
@@ -8,49 +8,57 @@
# RUN: | llvm-readobj -r - | FileCheck -check-prefix=NORELAX-RELOC %s
.long foo
+# NORELAX-RELOC: R_RISCV_32 foo 0x0
+# RELAX-RELOC: R_RISCV_32 foo 0x0
call foo
-# NORELAX-RELOC: R_RISCV_CALL_PLT foo 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_CALL_PLT foo 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_CALL_PLT foo 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_CALL_PLT foo 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
+
+jal foo
+# NORELAX-RELOC-NEXT: R_RISCV_JAL foo 0x0
+# NORELAX-RELOC-NOT: R_RISCV_RELAX
+# RELAX-RELOC-NEXT: R_RISCV_JAL foo 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
lui t1, %hi(foo)
-# NORELAX-RELOC: R_RISCV_HI20 foo 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_HI20 foo 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_HI20 foo 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_HI20 foo 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
addi t1, t1, %lo(foo)
-# NORELAX-RELOC: R_RISCV_LO12_I foo 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_LO12_I foo 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_LO12_I foo 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_LO12_I foo 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
sb t1, %lo(foo)(a2)
-# NORELAX-RELOC: R_RISCV_LO12_S foo 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_LO12_S foo 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_LO12_S foo 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_LO12_S foo 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
1:
auipc t1, %pcrel_hi(foo)
-# NORELAX-RELOC: R_RISCV_PCREL_HI20 foo 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_PCREL_HI20 foo 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_PCREL_HI20 foo 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_PCREL_HI20 foo 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
addi t1, t1, %pcrel_lo(1b)
-# NORELAX-RELOC: R_RISCV_PCREL_LO12_I .Ltmp0 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_PCREL_LO12_I .Ltmp0 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
sb t1, %pcrel_lo(1b)(a2)
-# NORELAX-RELOC: R_RISCV_PCREL_LO12_S .Ltmp0 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_S .Ltmp0 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_PCREL_LO12_S .Ltmp0 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_S .Ltmp0 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
# Check behaviour when a locally defined symbol is referenced.
@@ -63,64 +71,88 @@ call bar
# NORELAX-RELOC-NOT: R_RISCV_CALL
# NORELAX-RELOC-NOT: R_RISCV_RELAX
# RELAX-RELOC-NEXT: R_RISCV_CALL_PLT bar 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
+
+jal bar
+# NORELAX-RELOC-NOT: R_RISCV_JAL
+# NORELAX-RELOC-NOT: R_RISCV_RELAX
+# RELAX-RELOC-NEXT: R_RISCV_JAL bar 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
beq s1, s1, bar
# NORELAX-RELOC-NOT: R_RISCV_BRANCH
# RELAX-RELOC-NEXT: R_RISCV_BRANCH bar 0x0
lui t1, %hi(bar)
-# NORELAX-RELOC: R_RISCV_HI20 bar 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_HI20 bar 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_HI20 bar 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_HI20 bar 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
addi t1, t1, %lo(bar)
-# NORELAX-RELOC: R_RISCV_LO12_I bar 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_LO12_I bar 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_LO12_I bar 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_LO12_I bar 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
sb t1, %lo(bar)(a2)
-# NORELAX-RELOC: R_RISCV_LO12_S bar 0x0
+# NORELAX-RELOC-NEXT: R_RISCV_LO12_S bar 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_LO12_S bar 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_LO12_S bar 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
2:
auipc t1, %pcrel_hi(bar)
# NORELAX-RELOC-NOT: R_RISCV_PCREL_HI20
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_PCREL_HI20 bar 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_PCREL_HI20 bar 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
addi t1, t1, %pcrel_lo(2b)
# NORELAX-RELOC-NOT: R_RISCV_PCREL_LO12_I
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_PCREL_LO12_I .Ltmp1 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp1 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
sb t1, %pcrel_lo(2b)(a2)
# NORELAX-RELOC-NOT: R_RISCV_PCREL_LO12_S
# NORELAX-RELOC-NOT: R_RISCV_RELAX
-# RELAX-RELOC: R_RISCV_PCREL_LO12_S .Ltmp1 0x0
-# RELAX-RELOC: R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_S .Ltmp1 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
+
+auipc t1, %got_pcrel_hi(bar)
+# NORELAX-RELOC-NEXT: R_RISCV_GOT_HI20 bar 0x0
+# NORELAX-RELOC-NOT: R_RISCV_RELAX
+# RELAX-RELOC-NEXT: R_RISCV_GOT_HI20 bar 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
+
+lui t1, %tprel_hi(baz)
+# NORELAX-RELOC-NEXT: R_RISCV_TPREL_HI20 baz 0x0
+# NORELAX-RELOC-NOT: R_RISCV_RELAX
+# RELAX-RELOC-NEXT: R_RISCV_TPREL_HI20 baz 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
+
+auipc t1, %tlsdesc_hi(baz)
+# NORELAX-RELOC-NEXT: R_RISCV_TLSDESC_HI20 baz 0x0
+# NORELAX-RELOC-NOT: R_RISCV_RELAX
+# RELAX-RELOC-NEXT: R_RISCV_TLSDESC_HI20 baz 0x0
+# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
## %hi/%lo on an absolute symbol (not yet defined) leads to relocations when relaxation is enabled.
lui t2, %hi(abs)
# NORELAX-RELOC-NOT: R_RISCV_
-# RELAX-RELOC: R_RISCV_HI20 - 0x12345
+# RELAX-RELOC-NEXT: R_RISCV_HI20 - 0x12345
# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
addi t2, t2, %lo(abs)
# NORELAX-RELOC-NOT: R_RISCV_
-# RELAX-RELOC: R_RISCV_LO12_I - 0x12345
+# RELAX-RELOC-NEXT: R_RISCV_LO12_I - 0x12345
# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
.set abs, 0x12345
lui t3, %hi(abs)
-# RELAX-RELOC: R_RISCV_HI20 - 0x12345
+# RELAX-RELOC-NEXT: R_RISCV_HI20 - 0x12345
# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
# Check that a relocation is not emitted for a symbol difference which has
>From c9c3edfc3343321ec7d79084d92eb597b662194a Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Wed, 30 Jul 2025 17:42:17 -0700
Subject: [PATCH 2/7] Fix Tests, Relaxation
---
.../Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 10 ++++++++--
llvm/test/MC/RISCV/Relocations/expr.s | 2 ++
llvm/test/MC/RISCV/compressed-relocations.s | 4 +++-
llvm/test/MC/RISCV/option-relax.s | 1 +
llvm/test/MC/RISCV/xqcibi-relocations.s | 2 ++
5 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index c7135c8e7ab7f..3ec7ce549d950 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -340,8 +340,11 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
// Drop any fixup added so we can add the correct one.
Fixups.resize(FixupStartIndex);
- if (SrcSymbol.isExpr())
+ if (SrcSymbol.isExpr()) {
addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
+ if (STI.hasFeature(RISCV::FeatureRelax))
+ Fixups.back().setLinkerRelaxable();
+ }
}
// Expand PseudoLongQC_(E_)Bxxx to an inverted conditional branch and an
@@ -388,8 +391,11 @@ void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI,
support::endian::write(CB, JBinary, llvm::endianness::little);
// Drop any fixup added so we can add the correct one.
Fixups.resize(FixupStartIndex);
- if (SrcSymbol.isExpr())
+ if (SrcSymbol.isExpr()) {
addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
+ if (STI.hasFeature(RISCV::FeatureRelax))
+ Fixups.back().setLinkerRelaxable();
+ }
}
void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,
diff --git a/llvm/test/MC/RISCV/Relocations/expr.s b/llvm/test/MC/RISCV/Relocations/expr.s
index 7d4dfd30e3fb7..c26ef98f653fb 100644
--- a/llvm/test/MC/RISCV/Relocations/expr.s
+++ b/llvm/test/MC/RISCV/Relocations/expr.s
@@ -14,6 +14,7 @@ call relax
jal zero, .LBB0+16
# CHECK-INSTR: jal zero, 0x10
# CHECK-RELOC: R_RISCV_JAL
+# CHECK-RELOC-NEXT: R_RISCV_RELAX
beq a0, a1, .LBB1+32
# CHECK-INSTR: beq a0, a1, 0x20
@@ -31,4 +32,5 @@ c.beqz a0, .-2
call relax
# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT
+# CHECK-RELOC-NEXT: R_RISCV_RELAX
.LBB2:
diff --git a/llvm/test/MC/RISCV/compressed-relocations.s b/llvm/test/MC/RISCV/compressed-relocations.s
index 82cb1a12c389b..ba57507d0b4e8 100644
--- a/llvm/test/MC/RISCV/compressed-relocations.s
+++ b/llvm/test/MC/RISCV/compressed-relocations.s
@@ -3,7 +3,7 @@
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
-# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s
+# RUN: | llvm-readobj -r - | FileCheck -check-prefixes=RELOC,RELAX %s
# Check prefixes:
# RELOC - Check the relocation in the object.
@@ -11,10 +11,12 @@
c.jal foo
# A compressed jump (c.j) to an unresolved symbol will be relaxed to a (jal).
# RELOC: R_RISCV_JAL
+# RELAX-NEXT: R_RISCV_RELAX
# INSTR: c.jal foo
c.bnez a0, foo
# A compressed branch (c.bnez) to an unresolved symbol will be relaxed to a (bnez).
# The (bnez) to an unresolved symbol will in turn be relaxed to (beqz; jal)
# RELOC-NEXT: R_RISCV_JAL
+# RELAX-NEXT: R_RISCV_RELAX
# INSTR: c.bnez a0, foo
diff --git a/llvm/test/MC/RISCV/option-relax.s b/llvm/test/MC/RISCV/option-relax.s
index 55cdbeae01a4e..e591c824eb437 100644
--- a/llvm/test/MC/RISCV/option-relax.s
+++ b/llvm/test/MC/RISCV/option-relax.s
@@ -39,6 +39,7 @@ call bar
.dword .L2-.L1
# CHECK-RELOC-NEXT: R_RISCV_JAL
+# CHECK-RELOC-NEXT: R_RISCV_RELAX
jal zero, .L1
# CHECK-RELOC-NEXT: R_RISCV_BRANCH
beq s1, s1, .L1
diff --git a/llvm/test/MC/RISCV/xqcibi-relocations.s b/llvm/test/MC/RISCV/xqcibi-relocations.s
index 931cd7c9314bb..e613bc7bc4778 100644
--- a/llvm/test/MC/RISCV/xqcibi-relocations.s
+++ b/llvm/test/MC/RISCV/xqcibi-relocations.s
@@ -91,12 +91,14 @@ qc.e.bgeui s2, 24, same_section
# OBJ: qc.beqi t1, 0xa, 0x42 <same_section_extern+0x16>
# OBJ-NEXT: j 0x3e <same_section_extern+0x12>
# OBJ-NEXT: R_RISCV_JAL undef{{$}}
+# OBJ-NEXT: R_RISCV_RELAX *ABS*{{$}}
qc.bnei t1, 10, undef
# ASM: qc.e.bgeui s0, 40, undef
# OBJ-NEXT: qc.e.bltui s0, 0x28, 0x4c <same_section_extern+0x20>
# OBJ-NEXT: j 0x48 <same_section_extern+0x1c>
# OBJ-NEXT: R_RISCV_JAL undef{{$}}
+# OBJ-NEXT: R_RISCV_RELAX *ABS*{{$}}
qc.e.bgeui s0, 40, undef
.section .text.second, "ax", @progbits
>From 5f3d90ccfa889ef511d25e949b76d927f6683bb3 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Wed, 30 Jul 2025 20:58:56 -0700
Subject: [PATCH 3/7] Fix .option relax inline asm test
---
.../CodeGen/RISCV/option-relax-relocation.ll | 27 ++++++++++++++-----
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/option-relax-relocation.ll b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll
index fd3d9435e22a3..a6c65c816d3d8 100644
--- a/llvm/test/CodeGen/RISCV/option-relax-relocation.ll
+++ b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll
@@ -1,32 +1,45 @@
-;; With +relax, J below needs a relocation to ensure the target is correct
-;; after linker relaxation. See https://github.com/ClangBuiltLinux/linux/issues/1965
; RUN: llc -mtriple=riscv64 -mattr=-relax -filetype=obj < %s \
; RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefixes=CHECK,NORELAX
; RUN: llc -mtriple=riscv64 -mattr=+relax -filetype=obj < %s \
; RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefixes=CHECK,RELAX
+;; With +relax, All `j` instructions below need a relocation to ensure the target is correct
+;; after linker relaxation. See https://github.com/ClangBuiltLinux/linux/issues/1965
+
; CHECK: j {{.*}}
; RELAX-NEXT: R_RISCV_JAL {{.*}}
+; RELAX-NOT: R_RISCV_RELAX
; CHECK-NEXT: auipc ra, 0x0
; CHECK-NEXT: R_RISCV_CALL_PLT f
; RELAX-NEXT: R_RISCV_RELAX *ABS*
; CHECK-NEXT: jalr ra
; CHECK-NEXT: j {{.*}}
+; RELAX-NEXT: R_RISCV_JAL {{.*}}
+; RELAX-NOT: R_RISCV_RELAX
; CHECK-NEXT: j {{.*}}
-; RELAX-NEXT: R_RISCV_JAL .L0
+; RELAX-NEXT: R_RISCV_JAL {{.*}}
+; RELAX-NEXT: R_RISCV_RELAX *ABS*
; NORELAX-NEXT: li a0, 0x0
; RELAX-EMPTY:
define dso_local noundef signext i32 @main() local_unnamed_addr #0 {
entry:
- callbr void asm sideeffect ".option push\0A.option norelax\0Aj $0\0A.option pop\0A", "!i"()
- to label %asm.fallthrough [label %label]
+ callbr void asm sideeffect "
+ .option push
+ .option norelax
+ j $0
+ .option pop",
+ "!i"() to label %asm.fallthrough [label %label]
asm.fallthrough: ; preds = %entry
tail call void @f()
- callbr void asm sideeffect ".option push\0A.option norelax\0Aj $0\0A.option pop\0A", "!i"()
- to label %asm.fallthrough [label %label]
+ callbr void asm sideeffect "
+ .option push
+ .option norelax
+ j $0
+ .option pop",
+ "!i"() to label %asm.fallthrough [label %label]
br label %label
label: ; preds = %asm.fallthrough, %entry
>From 783c686ac72d01a5d917703972605593ac68f3ff Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 22 Aug 2025 17:08:58 -0700
Subject: [PATCH 4/7] Rework after merge
---
.../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 3 +-
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 23 +++++-----
.../CodeGen/RISCV/option-relax-relocation.ll | 1 -
llvm/test/MC/RISCV/Relocations/expr.s | 10 +++--
llvm/test/MC/RISCV/Relocations/relocations.s | 6 +++
llvm/test/MC/RISCV/align.s | 21 ++++++++--
llvm/test/MC/RISCV/long-conditional-jump.s | 42 ++++++++++++++++++-
llvm/test/MC/RISCV/tlsdesc.s | 25 +++++++++--
llvm/test/MC/RISCV/xqcibi-linker-relaxation.s | 8 ++--
9 files changed, 109 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index c69c8bfe00679..23bf4919a8f1f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -831,8 +831,9 @@ static bool relaxableFixupNeedsRelocation(const MCFixupKind Kind) {
default:
break;
case RISCV::fixup_riscv_rvc_jump:
+ case RISCV::fixup_riscv_branch:
case RISCV::fixup_riscv_rvc_branch:
- case RISCV::fixup_riscv_jal:
+ case RISCV::fixup_riscv_qc_e_branch:
return false;
}
return true;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index f94c5e1ff635e..4f56cf0601f8d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -204,6 +204,8 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
MCRegister Dest = MI.getOperand(1).getReg();
int64_t Imm = MI.getOperand(2).getImm();
addFixup(Fixups, 0, Expr, ELF::R_RISCV_TLSDESC_CALL);
+ if (STI.hasFeature(RISCV::FeatureRelax))
+ Fixups.back().setLinkerRelaxable();
MCInst Call =
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
@@ -595,10 +597,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
if (!STI.hasFeature(RISCV::FeatureExactAssembly))
RelaxCandidate = true;
};
- auto AsmRelaxToLinkerRelaxableWithFeature = [&](unsigned Feature) -> void {
- if (!STI.hasFeature(RISCV::FeatureExactAssembly) && STI.hasFeature(Feature))
- RelaxCandidate = true;
- };
unsigned FixupKind = RISCV::fixup_riscv_invalid;
if (Kind == MCExpr::Specifier) {
@@ -662,6 +660,9 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
case ELF::R_RISCV_GOT_HI20:
case ELF::R_RISCV_TPREL_HI20:
case ELF::R_RISCV_TLSDESC_HI20:
+ case ELF::R_RISCV_TLSDESC_LOAD_LO12:
+ case ELF::R_RISCV_TLSDESC_ADD_LO12:
+ case ELF::R_RISCV_TLSDESC_CALL:
RelaxCandidate = true;
break;
}
@@ -672,23 +673,24 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
RelaxCandidate = true;
} else if (MIFrm == RISCVII::InstFormatB) {
FixupKind = RISCV::fixup_riscv_branch;
- // This might be assembler relaxed to `b<cc>; jal` but we cannot relax
- // the `jal` again in the assembler.
+ // Relaxes to B<cc>; JAL, with fixup_riscv_jal
+ AsmRelaxToLinkerRelaxable();
} else if (MIFrm == RISCVII::InstFormatCJ) {
FixupKind = RISCV::fixup_riscv_rvc_jump;
+ // Relaxes to JAL with fixup_riscv_jal
AsmRelaxToLinkerRelaxable();
} else if (MIFrm == RISCVII::InstFormatCB) {
FixupKind = RISCV::fixup_riscv_rvc_branch;
- // This might be assembler relaxed to `b<cc>; jal` but we cannot relax
- // the `jal` again in the assembler.
+ // Relaxes to B<cc>; JAL, with fixup_riscv_jal
+ AsmRelaxToLinkerRelaxable();
} else if (MIFrm == RISCVII::InstFormatCI) {
FixupKind = RISCV::fixup_riscv_rvc_imm;
} else if (MIFrm == RISCVII::InstFormatI) {
FixupKind = RISCV::fixup_riscv_12_i;
} else if (MIFrm == RISCVII::InstFormatQC_EB) {
FixupKind = RISCV::fixup_riscv_qc_e_branch;
- // This might be assembler relaxed to `qc.e.b<cc>; jal` but we cannot
- // relax the `jal` again in the assembler.
+ // Relaxes to QC.E.B<cc>I; JAL, with fixup_riscv_jal
+ AsmRelaxToLinkerRelaxable();
} else if (MIFrm == RISCVII::InstFormatQC_EAI) {
FixupKind = RISCV::fixup_riscv_qc_e_32;
RelaxCandidate = true;
@@ -706,6 +708,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
// If linker relaxation is enabled and supported by this relocation, set a bit
// so that the assembler knows the size of the instruction is not fixed/known,
// and the relocation will need a R_RISCV_RELAX relocation.
+ LLVM_DEBUG(dbgs() << "Maybe Marking Fixup " << Fixups.back().getKind() << " as Relaxable " << EnableRelax << " " << RelaxCandidate << "\n");
if (EnableRelax && RelaxCandidate)
Fixups.back().setLinkerRelaxable();
++MCNumFixups;
diff --git a/llvm/test/CodeGen/RISCV/option-relax-relocation.ll b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll
index a6c65c816d3d8..62178e11f8713 100644
--- a/llvm/test/CodeGen/RISCV/option-relax-relocation.ll
+++ b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll
@@ -1,4 +1,3 @@
-
; RUN: llc -mtriple=riscv64 -mattr=-relax -filetype=obj < %s \
; RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefixes=CHECK,NORELAX
; RUN: llc -mtriple=riscv64 -mattr=+relax -filetype=obj < %s \
diff --git a/llvm/test/MC/RISCV/Relocations/expr.s b/llvm/test/MC/RISCV/Relocations/expr.s
index c26ef98f653fb..af55462f6d553 100644
--- a/llvm/test/MC/RISCV/Relocations/expr.s
+++ b/llvm/test/MC/RISCV/Relocations/expr.s
@@ -10,10 +10,12 @@
## This is linker-relaxable to avoid resolving the following fixups
call relax
+# CHECK-RELOC: R_RISCV_CALL_PLT
+# CHECK-RELOC-NEXT: R_RISCV_RELAX
jal zero, .LBB0+16
# CHECK-INSTR: jal zero, 0x10
-# CHECK-RELOC: R_RISCV_JAL
+# CHECK-RELOC-NEXT: R_RISCV_JAL
# CHECK-RELOC-NEXT: R_RISCV_RELAX
beq a0, a1, .LBB1+32
@@ -25,12 +27,12 @@ c.j .+32
c.j .LBB2+4
# CHECK-INSTR: c.j 0x22
-# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP
+# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP
c.beqz a0, .-2
# CHECK-INSTR: c.beqz a0, 0x12
call relax
-# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT
-# CHECK-RELOC-NEXT: R_RISCV_RELAX
+# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT
+# CHECK-RELOC-NEXT: R_RISCV_RELAX
.LBB2:
diff --git a/llvm/test/MC/RISCV/Relocations/relocations.s b/llvm/test/MC/RISCV/Relocations/relocations.s
index e1d56885aaf3b..42cdfe338fe54 100644
--- a/llvm/test/MC/RISCV/Relocations/relocations.s
+++ b/llvm/test/MC/RISCV/Relocations/relocations.s
@@ -2,19 +2,25 @@
# RUN: | FileCheck -check-prefix=INSTR %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c %s \
# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax %s \
+# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC-RELAX %s
# Check prefixes:
# RELOC - Check the relocation in the object.
+# RELOC-RELAX - Check the relocation in the object with relaxations
# INSTR - Check the instruction is handled properly by the ASMPrinter
.long foo
# RELOC: R_RISCV_32 foo
+# RELOC-RELAX: R_RISCV_32 foo
.quad foo
# RELOC: R_RISCV_64 foo
+# RELOC-RELAX: R_RISCV_64 foo
lui t1, %hi(foo)
# RELOC: R_RISCV_HI20 foo 0x0
+# RELOC
# INSTR: lui t1, %hi(foo)
lui t1, %hi(foo+4)
diff --git a/llvm/test/MC/RISCV/align.s b/llvm/test/MC/RISCV/align.s
index 4d4d998c992fd..92862d903ce14 100644
--- a/llvm/test/MC/RISCV/align.s
+++ b/llvm/test/MC/RISCV/align.s
@@ -137,8 +137,14 @@ data2:
add a0, a0, a1
## Branches crossing the linker-relaxable R_RISCV_ALIGN need relocations.
-# RELAX-RELOC-NOT: .rela.text3 {
-# C-OR-ZCA-EXT-RELAX-RELOC-NOT: .rela.text3 {
+# RELAX-RELOC: .rela.text3 {
+# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6
+# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: }
+# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3 {
.section .text3, "ax"
bnez t1, 1f
bnez t2, 2f
@@ -153,9 +159,11 @@ data2:
# RELAX-RELOC: .rela.text3a {
# RELAX-RELOC-NEXT: 0x0 R_RISCV_CALL_PLT foo 0x0
# RELAX-RELOC-NEXT: 0x0 R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: 0x8 R_RISCV_BRANCH .Ltmp[[#]] 0x0
# RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0
# RELAX-RELOC-NEXT: 0x10 R_RISCV_ALIGN - 0x6
# RELAX-RELOC-NEXT: 0x16 R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x1A R_RISCV_BRANCH .Ltmp[[#]] 0x0
# RELAX-RELOC-NEXT: }
# C-OR-ZCA-EXT-NORELAX-RELOC: .rela.text3a
# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3a
@@ -171,8 +179,13 @@ bnez t1, 2b
## .text3 with a call at the end
# RELAX-RELOC: .rela.text3b {
-# RELAX-RELOC-NEXT: 0x10 R_RISCV_CALL_PLT foo 0x0
-# RELAX-RELOC-NEXT: 0x10 R_RISCV_RELAX - 0x0
+# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6
+# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0
+# RELAX-RELOC-NEXT: 0x16 R_RISCV_CALL_PLT foo 0x0
+# RELAX-RELOC-NEXT: 0x16 R_RISCV_RELAX - 0x0
# RELAX-RELOC-NEXT: }
.section .text3b, "ax"
bnez t1, 1f
diff --git a/llvm/test/MC/RISCV/long-conditional-jump.s b/llvm/test/MC/RISCV/long-conditional-jump.s
index 5f10baed49829..db060bafccaa6 100644
--- a/llvm/test/MC/RISCV/long-conditional-jump.s
+++ b/llvm/test/MC/RISCV/long-conditional-jump.s
@@ -1,8 +1,8 @@
# RUN: llvm-mc -filetype=obj -triple=riscv64 %s \
-# RUN: | llvm-objdump -d -M no-aliases - \
+# RUN: | llvm-objdump -dr -M no-aliases - \
# RUN: | FileCheck --check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c %s \
-# RUN: | llvm-objdump -d -M no-aliases - \
+# RUN: | llvm-objdump -dr -M no-aliases - \
# RUN: | FileCheck --check-prefix=CHECK-INST-C %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s \
# RUN: | llvm-objdump -dr -M no-aliases - \
@@ -21,9 +21,11 @@ test:
# CHECK-INST-RELAX: beq a0, a1, 0x8
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L1
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: beq a0, a1, 0x8
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L1
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
bne a0, a1, .L1
call relax
.fill 1300-2, 4, 0
@@ -35,8 +37,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0x28b2
# CHECK-INST-RELAX: bne a0, a1, 0x1464
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L2
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: bne a0, a1, 0x1462
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L2
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
beq a0, a1, .L2
.fill 1300, 4, 0
.L2:
@@ -47,8 +53,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0x3d0c
# CHECK-INST-RELAX: bge a0, a1, 0x28c0
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L3
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: bge a0, a1, 0x28bc
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L3
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
blt a0, a1, .L3
.fill 1300, 4, 0
.L3:
@@ -59,8 +69,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0x5166
# CHECK-INST-RELAX: blt a0, a1, 0x3d1c
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L4
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: blt a0, a1, 0x3d16
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L4
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
bge a0, a1, .L4
.fill 1300, 4, 0
.L4:
@@ -71,8 +85,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0x65c0
# CHECK-INST-RELAX: bgeu a0, a1, 0x5178
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L5
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: bgeu a0, a1, 0x5170
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L5
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
bltu a0, a1, .L5
.fill 1300, 4, 0
.L5:
@@ -83,8 +101,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0x7a1a
# CHECK-INST-RELAX: bltu a0, a1, 0x65d4
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L6
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: bltu a0, a1, 0x65ca
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L6
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
bgeu a0, a1, .L6
.fill 1300, 4, 0
.L6:
@@ -95,8 +117,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0x8e72
# CHECK-INST-RELAX: bne a0, zero, 0x7a30
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L7
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: c.bnez a0, 0x7a22
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L7
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
beqz a0, .L7
.fill 1300, 4, 0
.L7:
@@ -107,8 +133,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0xa2ca
# CHECK-INST-RELAX: bne zero, a0, 0x8e8c
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L8
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: c.bnez a0, 0x8e7a
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L8
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
beq x0, a0, .L8
.fill 1300, 4, 0
.L8:
@@ -119,8 +149,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0xb722
# CHECK-INST-RELAX: beq a0, zero, 0xa2e8
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L9
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: c.beqz a0, 0xa2d2
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L9
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
bnez a0, .L9
.fill 1300, 4, 0
.L9:
@@ -131,8 +165,12 @@ test:
# CHECK-INST-C-NEXT: jal zero, 0xcb7c
# CHECK-INST-RELAX: beq a6, zero, 0xb744
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L10
+# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
# CHECK-INST-C-RELAX: beq a6, zero, 0xb72c
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
+# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L10
+# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
bnez x16, .L10
.fill 1300, 4, 0
.L10:
diff --git a/llvm/test/MC/RISCV/tlsdesc.s b/llvm/test/MC/RISCV/tlsdesc.s
index 675b01ac0225f..8db7c119ebefe 100644
--- a/llvm/test/MC/RISCV/tlsdesc.s
+++ b/llvm/test/MC/RISCV/tlsdesc.s
@@ -1,8 +1,20 @@
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s --defsym RV32=1 | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV32
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV64
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s --defsym RV32=1 \
+# RUN: | llvm-objdump -dr -M no-aliases - \
+# RUN: | FileCheck %s --check-prefixes=INST,RV32
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN: | llvm-objdump -dr -M no-aliases - \
+# RUN: | FileCheck %s --check-prefixes=INST,RV64
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s --defsym RV32=1 \
+# RUN: | llvm-objdump -dr -M no-aliases - \
+# RUN: | FileCheck %s --check-prefixes=INST,RV32,RELAX
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+relax < %s \
+# RUN: | llvm-objdump -dr -M no-aliases - \
+# RUN: | FileCheck %s --check-prefixes=INST,RV64,RELAX
-# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR
-# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR
+# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 \
+# RUN: | FileCheck %s --check-prefixes=ERR
+# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 \
+# RUN: | FileCheck %s --check-prefixes=ERR
start: # @start
# %bb.0: # %entry
@@ -10,9 +22,11 @@ start: # @start
auipc a0, %tlsdesc_hi(a-4)
# INST: auipc a0, 0x0
# INST-NEXT: R_RISCV_TLSDESC_HI20 a-0x4
+ # RELAX-NEXT: R_RISCV_RELAX
auipc a0, %tlsdesc_hi(unspecified)
# INST-NEXT: auipc a0, 0x0
# INST-NEXT: R_RISCV_TLSDESC_HI20 unspecified
+ # RELAX-NEXT: R_RISCV_RELAX
.ifdef RV32
lw a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0)
# RV32: lw a1, 0x0(a0)
@@ -22,12 +36,15 @@ start: # @start
# RV64: ld a1, 0x0(a0)
# RV64-NEXT: R_RISCV_TLSDESC_LOAD_LO12 .Ltlsdesc_hi0
.endif
+ # RELAX-NEXT: R_RISCV_RELAX
addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0)
# INST: addi a0, a0, 0x0
# INST-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi0
+ # RELAX-NEXT: R_RISCV_RELAX
jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0)
# INST-NEXT: jalr t0, 0x0(a1)
# INST-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi0
+ # RELAX-NEXT: R_RISCV_RELAX
add a0, a0, tp
# INST-NEXT: add a0, a0, tp
ret
diff --git a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s
index 2066b55b41ad3..4bcf4ffec7aea 100644
--- a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s
+++ b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s
@@ -61,9 +61,9 @@ mid_jump_over_fixed:
.space 0x1000
# CHECK-NEXT: ...
j mid_jump_over_fixed
-# CHECK-NEXT: jal zero, 0x24 <mid_jump_over_fixed>
-# CHECK-NOT: R_RISCV_JAL
-# CHECK-NOT: R_RISCV_RELAX
+# CHECK-NEXT: jal zero, 0x1026 <mid_jump_over_fixed+0x1002>
+# CHECK-NEXT: R_RISCV_JAL mid_jump_over_fixed
+# CHECK-NEXT: R_RISCV_RELAX *ABS*
ret
# CHECK-NEXT: c.jr ra
@@ -79,6 +79,6 @@ mid_jump_over_relaxable:
j mid_jump_over_relaxable
# CHECK-NEXT: jal zero, 0x2034 <mid_jump_over_relaxable+0x1008>
# CHECK-NEXT: R_RISCV_JAL mid_jump_over_relaxable
-# CHECK-NOT: R_RISCV_RELAX
+# CHECK-NEXT: R_RISCV_RELAX
ret
# CHECK-NEXT: c.jr ra
>From 673cd146c36f1a49b8f69eab8028fe1685be6c2e Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 22 Aug 2025 17:09:50 -0700
Subject: [PATCH 5/7] Remove debug
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 4f56cf0601f8d..ac23980aa95c0 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -708,7 +708,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
// If linker relaxation is enabled and supported by this relocation, set a bit
// so that the assembler knows the size of the instruction is not fixed/known,
// and the relocation will need a R_RISCV_RELAX relocation.
- LLVM_DEBUG(dbgs() << "Maybe Marking Fixup " << Fixups.back().getKind() << " as Relaxable " << EnableRelax << " " << RelaxCandidate << "\n");
if (EnableRelax && RelaxCandidate)
Fixups.back().setLinkerRelaxable();
++MCNumFixups;
>From 4170922f65834a4706e92d249d28641ddb61dc5a Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Fri, 22 Aug 2025 23:35:26 -0700
Subject: [PATCH 6/7] Undo TLSDESC changes
For the moment, while the abi discussion continues.
---
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 4 ---
llvm/test/MC/RISCV/linker-relaxation.s | 1 -
llvm/test/MC/RISCV/tlsdesc.s | 25 +++----------------
3 files changed, 4 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index ac23980aa95c0..4ee5b126047fe 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -659,10 +659,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
break;
case ELF::R_RISCV_GOT_HI20:
case ELF::R_RISCV_TPREL_HI20:
- case ELF::R_RISCV_TLSDESC_HI20:
- case ELF::R_RISCV_TLSDESC_LOAD_LO12:
- case ELF::R_RISCV_TLSDESC_ADD_LO12:
- case ELF::R_RISCV_TLSDESC_CALL:
RelaxCandidate = true;
break;
}
diff --git a/llvm/test/MC/RISCV/linker-relaxation.s b/llvm/test/MC/RISCV/linker-relaxation.s
index c5c4e4877ff2e..3257b6ff4926b 100644
--- a/llvm/test/MC/RISCV/linker-relaxation.s
+++ b/llvm/test/MC/RISCV/linker-relaxation.s
@@ -136,7 +136,6 @@ auipc t1, %tlsdesc_hi(baz)
# NORELAX-RELOC-NEXT: R_RISCV_TLSDESC_HI20 baz 0x0
# NORELAX-RELOC-NOT: R_RISCV_RELAX
# RELAX-RELOC-NEXT: R_RISCV_TLSDESC_HI20 baz 0x0
-# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0
## %hi/%lo on an absolute symbol (not yet defined) leads to relocations when relaxation is enabled.
lui t2, %hi(abs)
diff --git a/llvm/test/MC/RISCV/tlsdesc.s b/llvm/test/MC/RISCV/tlsdesc.s
index 8db7c119ebefe..675b01ac0225f 100644
--- a/llvm/test/MC/RISCV/tlsdesc.s
+++ b/llvm/test/MC/RISCV/tlsdesc.s
@@ -1,20 +1,8 @@
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s --defsym RV32=1 \
-# RUN: | llvm-objdump -dr -M no-aliases - \
-# RUN: | FileCheck %s --check-prefixes=INST,RV32
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -dr -M no-aliases - \
-# RUN: | FileCheck %s --check-prefixes=INST,RV64
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s --defsym RV32=1 \
-# RUN: | llvm-objdump -dr -M no-aliases - \
-# RUN: | FileCheck %s --check-prefixes=INST,RV32,RELAX
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+relax < %s \
-# RUN: | llvm-objdump -dr -M no-aliases - \
-# RUN: | FileCheck %s --check-prefixes=INST,RV64,RELAX
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s --defsym RV32=1 | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV32
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV64
-# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 \
-# RUN: | FileCheck %s --check-prefixes=ERR
-# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 \
-# RUN: | FileCheck %s --check-prefixes=ERR
+# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR
+# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR
start: # @start
# %bb.0: # %entry
@@ -22,11 +10,9 @@ start: # @start
auipc a0, %tlsdesc_hi(a-4)
# INST: auipc a0, 0x0
# INST-NEXT: R_RISCV_TLSDESC_HI20 a-0x4
- # RELAX-NEXT: R_RISCV_RELAX
auipc a0, %tlsdesc_hi(unspecified)
# INST-NEXT: auipc a0, 0x0
# INST-NEXT: R_RISCV_TLSDESC_HI20 unspecified
- # RELAX-NEXT: R_RISCV_RELAX
.ifdef RV32
lw a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0)
# RV32: lw a1, 0x0(a0)
@@ -36,15 +22,12 @@ start: # @start
# RV64: ld a1, 0x0(a0)
# RV64-NEXT: R_RISCV_TLSDESC_LOAD_LO12 .Ltlsdesc_hi0
.endif
- # RELAX-NEXT: R_RISCV_RELAX
addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0)
# INST: addi a0, a0, 0x0
# INST-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi0
- # RELAX-NEXT: R_RISCV_RELAX
jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0)
# INST-NEXT: jalr t0, 0x0(a1)
# INST-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi0
- # RELAX-NEXT: R_RISCV_RELAX
add a0, a0, tp
# INST-NEXT: add a0, a0, tp
ret
>From d3486bb6ad582fca02e5a034be58dac49e1aeb69 Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Sat, 23 Aug 2025 12:16:17 -0700
Subject: [PATCH 7/7] Fix bolt test
---
bolt/test/RISCV/reloc-label-diff.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bolt/test/RISCV/reloc-label-diff.s b/bolt/test/RISCV/reloc-label-diff.s
index f1144767714b1..4f2eb00322c6a 100644
--- a/bolt/test/RISCV/reloc-label-diff.s
+++ b/bolt/test/RISCV/reloc-label-diff.s
@@ -12,7 +12,7 @@ _start:
// BOLT removes this nop so the label difference is initially 8 but should be
// 4 after BOLT processes it.
nop
- beq x0, x0, _test_end
+ li x0, _test_end-.
_test_end:
ret
.size _start, .-_start
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