[llvm] [NFC][MC][ARM] Rearrange decode functions in ARM disassembler (PR #154988)
Rahul Joshi via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 22 10:12:46 PDT 2025
https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/154988
Rearrange decode functions to be before including the generated disassembler code and eliminate forward declarations for most of them. This is possible because `fieldFromInstruction` now in MCDecoder.h and not in the generated disassembler code.
>From 932988439c1f5bf6b0491026703d5178847b3f28 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Fri, 22 Aug 2025 10:01:37 -0700
Subject: [PATCH] [NFC][MC][ARM] Rearrange decode functions in ARM disassembler
Rearrange decode functions to be before including the generated
disassembler code and eliminate forward declarations for most of
them. This is possible because `fieldFromInstruction` now in
MCDecoder.h and not in the generated disassembler code.
---
.../ARM/Disassembler/ARMDisassembler.cpp | 5157 ++++++++---------
1 file changed, 2355 insertions(+), 2802 deletions(-)
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 19fa03cdc668d..6407b38999648 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -159,1132 +159,76 @@ class ARMDisassembler : public MCDisassembler {
} // end anonymous namespace
-// Forward declare these because the autogenerated code will reference them.
-// Definitions are further down.
-static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
- const MCDisassembler *Decoder);
-
-static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-
-static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-
-static DecodeStatus
-DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Adddress,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <int shift>
-static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-
-static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-template <int shift>
-static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <int shift>
-static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <int shift, int WriteBack>
-static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-
-static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-
-template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
-static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-template <bool Writeback>
-static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <int shift>
-static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <int shift>
-static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <int shift>
-static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <unsigned MinLog, unsigned MaxLog>
-static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <unsigned start>
-static DecodeStatus
-DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder);
-template <bool scalar, OperandDecoder predicate_decoder>
-static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus
-DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder);
-
-#include "ARMGenDisassemblerTables.inc"
-
-static MCDisassembler *createARMDisassembler(const Target &T,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
- return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());
-}
-
-// Post-decoding checks
-static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
- uint64_t Address, raw_ostream &CS,
- uint32_t Insn,
- DecodeStatus Result) {
- switch (MI.getOpcode()) {
- case ARM::HVC: {
- // HVC is undefined if condition = 0xf otherwise upredictable
- // if condition != 0xe
- uint32_t Cond = (Insn >> 28) & 0xF;
- if (Cond == 0xF)
- return MCDisassembler::Fail;
- if (Cond != 0xE)
- return MCDisassembler::SoftFail;
- return Result;
- }
- case ARM::t2ADDri:
- case ARM::t2ADDri12:
- case ARM::t2ADDrr:
- case ARM::t2ADDrs:
- case ARM::t2SUBri:
- case ARM::t2SUBri12:
- case ARM::t2SUBrr:
- case ARM::t2SUBrs:
- if (MI.getOperand(0).getReg() == ARM::SP &&
- MI.getOperand(1).getReg() != ARM::SP)
- return MCDisassembler::SoftFail;
- return Result;
- default: return Result;
- }
-}
-
-uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
- uint64_t Address) const {
- // In Arm state, instructions are always 4 bytes wide, so there's no
- // point in skipping any smaller number of bytes if an instruction
- // can't be decoded.
- if (!STI.hasFeature(ARM::ModeThumb))
- return 4;
-
- // In a Thumb instruction stream, a halfword is a standalone 2-byte
- // instruction if and only if its value is less than 0xE800.
- // Otherwise, it's the first halfword of a 4-byte instruction.
- //
- // So, if we can see the upcoming halfword, we can judge on that
- // basis, and maybe skip a whole 4-byte instruction that we don't
- // know how to decode, without accidentally trying to interpret its
- // second half as something else.
- //
- // If we don't have the instruction data available, we just have to
- // recommend skipping the minimum sensible distance, which is 2
- // bytes.
- if (Bytes.size() < 2)
- return 2;
-
- uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
- Bytes.data(), InstructionEndianness);
- return Insn16 < 0xE800 ? 2 : 4;
-}
-
-DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
- ArrayRef<uint8_t> Bytes,
- uint64_t Address,
- raw_ostream &CS) const {
- if (STI.hasFeature(ARM::ModeThumb))
- return getThumbInstruction(MI, Size, Bytes, Address, CS);
- return getARMInstruction(MI, Size, Bytes, Address, CS);
-}
-
-DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
- ArrayRef<uint8_t> Bytes,
- uint64_t Address,
- raw_ostream &CS) const {
- CommentStream = &CS;
-
- assert(!STI.hasFeature(ARM::ModeThumb) &&
- "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
- "mode!");
-
- // We want to read exactly 4 bytes of data.
- if (Bytes.size() < 4) {
- Size = 0;
- return MCDisassembler::Fail;
- }
-
- // Encoded as a 32-bit word in the stream.
- uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),
- InstructionEndianness);
-
- // Calling the auto-generated decoder function.
- DecodeStatus Result =
- decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
- }
-
- struct DecodeTable {
- const uint8_t *P;
- bool DecodePred;
- };
-
- const DecodeTable Tables[] = {
- {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
- {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
- {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
- {DecoderTablev8Crypto32, false},
- };
-
- for (auto Table : Tables) {
- Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- // Add a fake predicate operand, because we share these instruction
- // definitions with Thumb2 where these instructions are predicable.
- if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
- return MCDisassembler::Fail;
- return Result;
- }
- }
-
- Result =
- decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
- }
-
- Size = 4;
- return MCDisassembler::Fail;
-}
-
-/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
-/// immediate Value in the MCInst. The immediate Value has had any PC
-/// adjustment made by the caller. If the instruction is a branch instruction
-/// then isBranch is true, else false. If the getOpInfo() function was set as
-/// part of the setupForSymbolicDisassembly() call then that function is called
-/// to get any symbolic information at the Address for this instruction. If
-/// that returns non-zero then the symbolic information it returns is used to
-/// create an MCExpr and that is added as an operand to the MCInst. If
-/// getOpInfo() returns zero and isBranch is true then a symbol look up for
-/// Value is done and if a symbol is found an MCExpr is created with that, else
-/// an MCExpr with Value is created. This function returns true if it adds an
-/// operand to the MCInst and false otherwise.
-static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
- bool isBranch, uint64_t InstSize,
- MCInst &MI,
- const MCDisassembler *Decoder) {
- // FIXME: Does it make sense for value to be negative?
- return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
- isBranch, /*Offset=*/0, /*OpSize=*/0,
- InstSize);
-}
-
-/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
-/// referenced by a load instruction with the base register that is the Pc.
-/// These can often be values in a literal pool near the Address of the
-/// instruction. The Address of the instruction and its immediate Value are
-/// used as a possible literal pool entry. The SymbolLookUp call back will
-/// return the name of a symbol referenced by the literal pool's entry if
-/// the referenced address is that of a symbol. Or it will return a pointer to
-/// a literal 'C' string if the referenced address of the literal pool's entry
-/// is an address into a section with 'C' string literals.
-static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
- const MCDisassembler *Decoder) {
- Decoder->tryAddingPcLoadReferenceComment(Value, Address);
-}
-
-// Thumb1 instructions don't have explicit S bits. Rather, they
-// implicitly set CPSR. Since it's not represented in the encoding, the
-// auto-generated decoder won't inject the CPSR operand. We need to fix
-// that as a post-pass.
-void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- MCInst::iterator I = MI.begin();
- for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) {
- if (I == MI.end()) break;
- if (MCID.operands()[i].isOptionalDef() &&
- MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
- if (i > 0 && MCID.operands()[i - 1].isPredicate())
- continue;
- MI.insert(I,
- MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
- return;
- }
- }
-
- MI.insert(I, MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
-}
-
-bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- for (unsigned i = 0; i < MCID.NumOperands; ++i) {
- if (ARM::isVpred(MCID.operands()[i].OperandType))
- return true;
- }
- return false;
-}
-
-// Most Thumb instructions don't have explicit predicates in the
-// encoding, but rather get their predicates from IT context. We need
-// to fix up the predicate operands using this context information as a
-// post-pass.
-MCDisassembler::DecodeStatus
-ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
- MCDisassembler::DecodeStatus S = Success;
-
- const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
-
- // A few instructions actually have predicates encoded in them. Don't
- // try to overwrite it if we're seeing one of those.
- switch (MI.getOpcode()) {
- case ARM::tBcc:
- case ARM::t2Bcc:
- case ARM::tCBZ:
- case ARM::tCBNZ:
- case ARM::tCPS:
- case ARM::t2CPS3p:
- case ARM::t2CPS2p:
- case ARM::t2CPS1p:
- case ARM::t2CSEL:
- case ARM::t2CSINC:
- case ARM::t2CSINV:
- case ARM::t2CSNEG:
- case ARM::tMOVSr:
- case ARM::tSETEND:
- // Some instructions (mostly conditional branches) are not
- // allowed in IT blocks.
- if (ITBlock.instrInITBlock())
- S = SoftFail;
- else
- return Success;
- break;
- case ARM::t2HINT:
- if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
- S = SoftFail;
- break;
- case ARM::tB:
- case ARM::t2B:
- case ARM::t2TBB:
- case ARM::t2TBH:
- // Some instructions (mostly unconditional branches) can
- // only appears at the end of, or outside of, an IT.
- if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
- S = SoftFail;
- break;
- default:
- break;
- }
-
- // Warn on non-VPT predicable instruction in a VPT block and a VPT
- // predicable instruction in an IT block
- if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||
- (isVectorPredicable(MI) && ITBlock.instrInITBlock()))
- S = SoftFail;
-
- // If we're in an IT/VPT block, base the predicate on that. Otherwise,
- // assume a predicate of AL.
- unsigned CC = ARMCC::AL;
- unsigned VCC = ARMVCC::None;
- if (ITBlock.instrInITBlock()) {
- CC = ITBlock.getITCC();
- ITBlock.advanceITState();
- } else if (VPTBlock.instrInVPTBlock()) {
- VCC = VPTBlock.getVPTPred();
- VPTBlock.advanceVPTState();
- }
-
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
-
- MCInst::iterator CCI = MI.begin();
- for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) {
- if (MCID.operands()[i].isPredicate() || CCI == MI.end())
- break;
- }
-
- if (MCID.isPredicable()) {
- CCI = MI.insert(CCI, MCOperand::createImm(CC));
- ++CCI;
- if (CC == ARMCC::AL)
- MI.insert(CCI, MCOperand::createReg(ARM::NoRegister));
- else
- MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
- } else if (CC != ARMCC::AL) {
- Check(S, SoftFail);
- }
-
- MCInst::iterator VCCI = MI.begin();
- unsigned VCCPos;
- for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) {
- if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end())
- break;
- }
-
- if (isVectorPredicable(MI)) {
- VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
- ++VCCI;
- if (VCC == ARMVCC::None)
- VCCI = MI.insert(VCCI, MCOperand::createReg(0));
- else
- VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
- ++VCCI;
- VCCI = MI.insert(VCCI, MCOperand::createReg(0));
- ++VCCI;
- if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
- int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO);
- assert(TiedOp >= 0 &&
- "Inactive register in vpred_r is not tied to an output!");
- // Copy the operand to ensure it's not invalidated when MI grows.
- MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
- }
- } else if (VCC != ARMVCC::None) {
- Check(S, SoftFail);
- }
-
- return S;
-}
-
-// Thumb VFP instructions are a special case. Because we share their
-// encodings between ARM and Thumb modes, and they are predicable in ARM
-// mode, the auto-generated decoder will give them an (incorrect)
-// predicate operand. We need to rewrite these operands based on the IT
-// context as a post-pass.
-void ARMDisassembler::UpdateThumbVFPPredicate(
- DecodeStatus &S, MCInst &MI) const {
- unsigned CC;
- CC = ITBlock.getITCC();
- if (CC == 0xF)
- CC = ARMCC::AL;
- if (ITBlock.instrInITBlock())
- ITBlock.advanceITState();
- else if (VPTBlock.instrInVPTBlock()) {
- CC = VPTBlock.getVPTPred();
- VPTBlock.advanceVPTState();
- }
-
- const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
- ArrayRef<MCOperandInfo> OpInfo = MCID.operands();
- MCInst::iterator I = MI.begin();
- unsigned short NumOps = MCID.NumOperands;
- for (unsigned i = 0; i < NumOps; ++i, ++I) {
- if (OpInfo[i].isPredicate() ) {
- if (CC != ARMCC::AL && !MCID.isPredicable())
- Check(S, SoftFail);
- I->setImm(CC);
- ++I;
- if (CC == ARMCC::AL)
- I->setReg(ARM::NoRegister);
- else
- I->setReg(ARM::CPSR);
- return;
- }
- }
-}
-
-DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
- ArrayRef<uint8_t> Bytes,
- uint64_t Address,
- raw_ostream &CS) const {
- CommentStream = &CS;
-
- assert(STI.hasFeature(ARM::ModeThumb) &&
- "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
-
- // We want to read exactly 2 bytes of data.
- if (Bytes.size() < 2) {
- Size = 0;
- return MCDisassembler::Fail;
- }
-
- uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
- Bytes.data(), InstructionEndianness);
- DecodeStatus Result =
- decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 2;
- Check(Result, AddThumbPredicate(MI));
- return Result;
- }
-
- Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
- STI);
- if (Result) {
- Size = 2;
- bool InITBlock = ITBlock.instrInITBlock();
- Check(Result, AddThumbPredicate(MI));
- AddThumb1SBit(MI, InITBlock);
- return Result;
- }
-
- Result =
- decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 2;
-
- // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
- // the Thumb predicate.
- if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
- Result = MCDisassembler::SoftFail;
-
- Check(Result, AddThumbPredicate(MI));
-
- // If we find an IT instruction, we need to parse its condition
- // code and mask operands so that we can apply them correctly
- // to the subsequent instructions.
- if (MI.getOpcode() == ARM::t2IT) {
- unsigned Firstcond = MI.getOperand(0).getImm();
- unsigned Mask = MI.getOperand(1).getImm();
- ITBlock.setITState(Firstcond, Mask);
-
- // An IT instruction that would give a 'NV' predicate is unpredictable.
- if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
- CS << "unpredictable IT predicate sequence";
- }
-
- return Result;
- }
-
- // We want to read exactly 4 bytes of data.
- if (Bytes.size() < 4) {
- Size = 0;
- return MCDisassembler::Fail;
- }
-
- uint32_t Insn32 =
- (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
- Bytes.data() + 2, InstructionEndianness);
-
- Result =
- decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
-
- // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
- // the VPT predicate.
- if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
- Result = MCDisassembler::SoftFail;
-
- Check(Result, AddThumbPredicate(MI));
-
- if (isVPTOpcode(MI.getOpcode())) {
- unsigned Mask = MI.getOperand(0).getImm();
- VPTBlock.setVPTState(Mask);
- }
-
- return Result;
- }
-
- Result =
- decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- bool InITBlock = ITBlock.instrInITBlock();
- Check(Result, AddThumbPredicate(MI));
- AddThumb1SBit(MI, InITBlock);
- return Result;
- }
-
- Result =
- decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- Check(Result, AddThumbPredicate(MI));
- return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
- }
-
- if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
- Result =
- decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- UpdateThumbVFPPredicate(Result, MI);
- return Result;
- }
- }
-
- Result =
- decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- return Result;
- }
-
- if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
- Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
- STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- Check(Result, AddThumbPredicate(MI));
- return Result;
- }
- }
-
- if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
- uint32_t NEONLdStInsn = Insn32;
- NEONLdStInsn &= 0xF0FFFFFF;
- NEONLdStInsn |= 0x04000000;
- Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
- Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- Check(Result, AddThumbPredicate(MI));
- return Result;
- }
- }
-
- if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
- uint32_t NEONDataInsn = Insn32;
- NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
- NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
- NEONDataInsn |= 0x12000000; // Set bits 28 and 25
- Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
- Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- Check(Result, AddThumbPredicate(MI));
- return Result;
- }
+static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder);
- uint32_t NEONCryptoInsn = Insn32;
- NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
- NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
- NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
- Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
- Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- return Result;
- }
+static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder);
- uint32_t NEONv8Insn = Insn32;
- NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
- Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
- this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- return Result;
- }
- }
+static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder);
- uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
- const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
- ? DecoderTableThumb2CDE32
- : DecoderTableThumb2CoProc32;
- Result =
- decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 4;
- Check(Result, AddThumbPredicate(MI));
- return Result;
- }
+static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder);
+typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder);
- // Advance IT state to prevent next instruction inheriting
- // the wrong IT state.
- if (ITBlock.instrInITBlock())
- ITBlock.advanceITState();
- Size = 0;
- return MCDisassembler::Fail;
+/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
+/// immediate Value in the MCInst. The immediate Value has had any PC
+/// adjustment made by the caller. If the instruction is a branch instruction
+/// then isBranch is true, else false. If the getOpInfo() function was set as
+/// part of the setupForSymbolicDisassembly() call then that function is called
+/// to get any symbolic information at the Address for this instruction. If
+/// that returns non-zero then the symbolic information it returns is used to
+/// create an MCExpr and that is added as an operand to the MCInst. If
+/// getOpInfo() returns zero and isBranch is true then a symbol look up for
+/// Value is done and if a symbol is found an MCExpr is created with that, else
+/// an MCExpr with Value is created. This function returns true if it adds an
+/// operand to the MCInst and false otherwise.
+static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
+ bool isBranch, uint64_t InstSize,
+ MCInst &MI,
+ const MCDisassembler *Decoder) {
+ // FIXME: Does it make sense for value to be negative?
+ return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
+ isBranch, /*Offset=*/0, /*OpSize=*/0,
+ InstSize);
}
-extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
-LLVMInitializeARMDisassembler() {
- TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
- createARMDisassembler);
- TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
- createARMDisassembler);
- TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
- createARMDisassembler);
- TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
- createARMDisassembler);
+/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
+/// referenced by a load instruction with the base register that is the Pc.
+/// These can often be values in a literal pool near the Address of the
+/// instruction. The Address of the instruction and its immediate Value are
+/// used as a possible literal pool entry. The SymbolLookUp call back will
+/// return the name of a symbol referenced by the literal pool's entry if
+/// the referenced address is that of a symbol. Or it will return a pointer to
+/// a literal 'C' string if the referenced address of the literal pool's entry
+/// is an address into a section with 'C' string literals.
+static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
+ const MCDisassembler *Decoder) {
+ Decoder->tryAddingPcLoadReferenceComment(Value, Address);
}
+// clang-format off
static const uint16_t GPRDecoderTable[] = {
- ARM::R0, ARM::R1, ARM::R2, ARM::R3,
- ARM::R4, ARM::R5, ARM::R6, ARM::R7,
- ARM::R8, ARM::R9, ARM::R10, ARM::R11,
- ARM::R12, ARM::SP, ARM::LR, ARM::PC
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R9, ARM::R10, ARM::R11,
+ ARM::R12, ARM::SP, ARM::LR, ARM::PC
};
static const uint16_t CLRMGPRDecoderTable[] = {
- ARM::R0, ARM::R1, ARM::R2, ARM::R3,
- ARM::R4, ARM::R5, ARM::R6, ARM::R7,
- ARM::R8, ARM::R9, ARM::R10, ARM::R11,
- ARM::R12, 0, ARM::LR, ARM::APSR
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R9, ARM::R10, ARM::R11,
+ ARM::R12, 0, ARM::LR, ARM::APSR
};
+// clang-format on
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
@@ -1342,8 +286,7 @@ DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- if (RegNo == 15)
- {
+ if (RegNo == 15) {
Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
return MCDisassembler::Success;
}
@@ -1357,8 +300,7 @@ DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- if (RegNo == 15)
- {
+ if (RegNo == 15) {
Inst.addOperand(MCOperand::createReg(ARM::ZR));
return MCDisassembler::Success;
}
@@ -1388,10 +330,12 @@ static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}
+// clang-format off
static const uint16_t GPRPairDecoderTable[] = {
ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
};
+// clang-format on
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
@@ -1404,9 +348,9 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Fail;
if (RegNo & 1)
- S = MCDisassembler::SoftFail;
+ S = MCDisassembler::SoftFail;
- unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
+ unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2];
Inst.addOperand(MCOperand::createReg(RegisterPair));
return S;
}
@@ -1417,11 +361,11 @@ DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
if (RegNo > 13)
return MCDisassembler::Fail;
- unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
+ unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2];
Inst.addOperand(MCOperand::createReg(RegisterPair));
if ((RegNo & 1) || RegNo > 10)
- return MCDisassembler::SoftFail;
+ return MCDisassembler::SoftFail;
return MCDisassembler::Success;
}
@@ -1482,16 +426,18 @@ static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
return S;
}
+// clang-format off
static const MCPhysReg SPRDecoderTable[] = {
- ARM::S0, ARM::S1, ARM::S2, ARM::S3,
- ARM::S4, ARM::S5, ARM::S6, ARM::S7,
- ARM::S8, ARM::S9, ARM::S10, ARM::S11,
- ARM::S12, ARM::S13, ARM::S14, ARM::S15,
- ARM::S16, ARM::S17, ARM::S18, ARM::S19,
- ARM::S20, ARM::S21, ARM::S22, ARM::S23,
- ARM::S24, ARM::S25, ARM::S26, ARM::S27,
- ARM::S28, ARM::S29, ARM::S30, ARM::S31
+ ARM::S0, ARM::S1, ARM::S2, ARM::S3,
+ ARM::S4, ARM::S5, ARM::S6, ARM::S7,
+ ARM::S8, ARM::S9, ARM::S10, ARM::S11,
+ ARM::S12, ARM::S13, ARM::S14, ARM::S15,
+ ARM::S16, ARM::S17, ARM::S18, ARM::S19,
+ ARM::S20, ARM::S21, ARM::S22, ARM::S23,
+ ARM::S24, ARM::S25, ARM::S26, ARM::S27,
+ ARM::S28, ARM::S29, ARM::S30, ARM::S31
};
+// clang-format on
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
@@ -1510,16 +456,18 @@ static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
}
+// clang-format off
static const MCPhysReg DPRDecoderTable[] = {
- ARM::D0, ARM::D1, ARM::D2, ARM::D3,
- ARM::D4, ARM::D5, ARM::D6, ARM::D7,
- ARM::D8, ARM::D9, ARM::D10, ARM::D11,
- ARM::D12, ARM::D13, ARM::D14, ARM::D15,
- ARM::D16, ARM::D17, ARM::D18, ARM::D19,
- ARM::D20, ARM::D21, ARM::D22, ARM::D23,
- ARM::D24, ARM::D25, ARM::D26, ARM::D27,
- ARM::D28, ARM::D29, ARM::D30, ARM::D31
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10, ARM::D11,
+ ARM::D12, ARM::D13, ARM::D14, ARM::D15,
+ ARM::D16, ARM::D17, ARM::D18, ARM::D19,
+ ARM::D20, ARM::D21, ARM::D22, ARM::D23,
+ ARM::D24, ARM::D25, ARM::D26, ARM::D27,
+ ARM::D28, ARM::D29, ARM::D30, ARM::D31
};
+// clang-format on
// Does this instruction/subtarget permit use of registers d16-d31?
static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {
@@ -1565,12 +513,14 @@ static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
}
+// clang-format off
static const MCPhysReg QPRDecoderTable[] = {
- ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
- ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
- ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
- ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
+ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
+ ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
+ ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
+ ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
};
+// clang-format on
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
@@ -1584,6 +534,54 @@ static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if (RegNo > 7)
+ return MCDisassembler::Fail;
+
+ unsigned Register = QPRDecoderTable[RegNo];
+ Inst.addOperand(MCOperand::createReg(Register));
+ return MCDisassembler::Success;
+}
+
+// clang-format off
+static const MCPhysReg QQPRDecoderTable[] = {
+ ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
+ ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
+};
+// clang-format on
+
+static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if (RegNo > 6)
+ return MCDisassembler::Fail;
+
+ unsigned Register = QQPRDecoderTable[RegNo];
+ Inst.addOperand(MCOperand::createReg(Register));
+ return MCDisassembler::Success;
+}
+
+// clang-format off
+static const MCPhysReg QQQQPRDecoderTable[] = {
+ ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
+ ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
+};
+// clang-format on
+
+static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if (RegNo > 4)
+ return MCDisassembler::Fail;
+
+ unsigned Register = QQQQPRDecoderTable[RegNo];
+ Inst.addOperand(MCOperand::createReg(Register));
+ return MCDisassembler::Success;
+}
+
+// clang-format off
static const MCPhysReg DPairDecoderTable[] = {
ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
@@ -1592,6 +590,7 @@ static const MCPhysReg DPairDecoderTable[] = {
ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
ARM::Q15
};
+// clang-format on
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
@@ -1604,6 +603,7 @@ static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}
+// clang-format off
static const MCPhysReg DPairSpacedDecoderTable[] = {
ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
@@ -1614,6 +614,7 @@ static const MCPhysReg DPairSpacedDecoderTable[] = {
ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
ARM::D28_D30, ARM::D29_D31
};
+// clang-format on
static DecodeStatus
DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
@@ -2760,28 +1761,6 @@ static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
return S;
}
-static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
-
- unsigned Pred = fieldFromInstruction(Insn, 28, 4);
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction(Insn, 0, 4);
-
- if (Pred == 0xF)
- return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
-
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
- return MCDisassembler::Fail;
-
- return S;
-}
-
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -2792,17 +1771,16 @@ static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
const FeatureBitset &FeatureBits =
Decoder->getSubtargetInfo().getFeatureBits();
- if (!FeatureBits[ARM::HasV8_1aOps] ||
- !FeatureBits[ARM::HasV8Ops])
+ if (!FeatureBits[ARM::HasV8_1aOps] || !FeatureBits[ARM::HasV8Ops])
return MCDisassembler::Fail;
// Decoder can be called from DecodeTST, which does not check the full
// encoding is valid.
- if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
- fieldFromInstruction(Insn, 4,4) != 0)
+ if (fieldFromInstruction(Insn, 20, 12) != 0xf11 ||
+ fieldFromInstruction(Insn, 4, 4) != 0)
return MCDisassembler::Fail;
- if (fieldFromInstruction(Insn, 10,10) != 0 ||
- fieldFromInstruction(Insn, 0,4) != 0)
+ if (fieldFromInstruction(Insn, 10, 10) != 0 ||
+ fieldFromInstruction(Insn, 0, 4) != 0)
S = MCDisassembler::SoftFail;
Inst.setOpcode(ARM::SETPAN);
@@ -2811,6 +1789,28 @@ static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
return S;
}
+static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Pred = fieldFromInstruction(Insn, 28, 4);
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction(Insn, 0, 4);
+
+ if (Pred == 0xF)
+ return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
+
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
+
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -3447,112 +2447,118 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
case ARM::VST2b8:
case ARM::VST2b16wb_fixed:
case ARM::VST2b16wb_register:
- case ARM::VST2b32wb_fixed:
- case ARM::VST2b32wb_register:
- case ARM::VST2b8wb_fixed:
- case ARM::VST2b8wb_register:
- if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- default:
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
- }
-
- // Second input register
- switch (Inst.getOpcode()) {
- case ARM::VST3d8:
- case ARM::VST3d16:
- case ARM::VST3d32:
- case ARM::VST3d8_UPD:
- case ARM::VST3d16_UPD:
- case ARM::VST3d32_UPD:
- case ARM::VST4d8:
- case ARM::VST4d16:
- case ARM::VST4d32:
- case ARM::VST4d8_UPD:
- case ARM::VST4d16_UPD:
- case ARM::VST4d32_UPD:
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- case ARM::VST3q8:
- case ARM::VST3q16:
- case ARM::VST3q32:
- case ARM::VST3q8_UPD:
- case ARM::VST3q16_UPD:
- case ARM::VST3q32_UPD:
- case ARM::VST4q8:
- case ARM::VST4q16:
- case ARM::VST4q32:
- case ARM::VST4q8_UPD:
- case ARM::VST4q16_UPD:
- case ARM::VST4q32_UPD:
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- default:
- break;
+ case ARM::VST2b32wb_fixed:
+ case ARM::VST2b32wb_register:
+ case ARM::VST2b8wb_fixed:
+ case ARM::VST2b8wb_register:
+ if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ default:
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+
+ // Second input register
+ switch (Inst.getOpcode()) {
+ case ARM::VST3d8:
+ case ARM::VST3d16:
+ case ARM::VST3d32:
+ case ARM::VST3d8_UPD:
+ case ARM::VST3d16_UPD:
+ case ARM::VST3d32_UPD:
+ case ARM::VST4d8:
+ case ARM::VST4d16:
+ case ARM::VST4d32:
+ case ARM::VST4d8_UPD:
+ case ARM::VST4d16_UPD:
+ case ARM::VST4d32_UPD:
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ case ARM::VST3q8:
+ case ARM::VST3q16:
+ case ARM::VST3q32:
+ case ARM::VST3q8_UPD:
+ case ARM::VST3q16_UPD:
+ case ARM::VST3q32_UPD:
+ case ARM::VST4q8:
+ case ARM::VST4q16:
+ case ARM::VST4q32:
+ case ARM::VST4q8_UPD:
+ case ARM::VST4q16_UPD:
+ case ARM::VST4q32_UPD:
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ default:
+ break;
}
// Third input register
switch (Inst.getOpcode()) {
- case ARM::VST3d8:
- case ARM::VST3d16:
- case ARM::VST3d32:
- case ARM::VST3d8_UPD:
- case ARM::VST3d16_UPD:
- case ARM::VST3d32_UPD:
- case ARM::VST4d8:
- case ARM::VST4d16:
- case ARM::VST4d32:
- case ARM::VST4d8_UPD:
- case ARM::VST4d16_UPD:
- case ARM::VST4d32_UPD:
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- case ARM::VST3q8:
- case ARM::VST3q16:
- case ARM::VST3q32:
- case ARM::VST3q8_UPD:
- case ARM::VST3q16_UPD:
- case ARM::VST3q32_UPD:
- case ARM::VST4q8:
- case ARM::VST4q16:
- case ARM::VST4q32:
- case ARM::VST4q8_UPD:
- case ARM::VST4q16_UPD:
- case ARM::VST4q32_UPD:
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- default:
- break;
+ case ARM::VST3d8:
+ case ARM::VST3d16:
+ case ARM::VST3d32:
+ case ARM::VST3d8_UPD:
+ case ARM::VST3d16_UPD:
+ case ARM::VST3d32_UPD:
+ case ARM::VST4d8:
+ case ARM::VST4d16:
+ case ARM::VST4d32:
+ case ARM::VST4d8_UPD:
+ case ARM::VST4d16_UPD:
+ case ARM::VST4d32_UPD:
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ case ARM::VST3q8:
+ case ARM::VST3q16:
+ case ARM::VST3q32:
+ case ARM::VST3q8_UPD:
+ case ARM::VST3q16_UPD:
+ case ARM::VST3q32_UPD:
+ case ARM::VST4q8:
+ case ARM::VST4q16:
+ case ARM::VST4q32:
+ case ARM::VST4q8_UPD:
+ case ARM::VST4q16_UPD:
+ case ARM::VST4q32_UPD:
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ default:
+ break;
}
// Fourth input register
switch (Inst.getOpcode()) {
- case ARM::VST4d8:
- case ARM::VST4d16:
- case ARM::VST4d32:
- case ARM::VST4d8_UPD:
- case ARM::VST4d16_UPD:
- case ARM::VST4d32_UPD:
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- case ARM::VST4q8:
- case ARM::VST4q16:
- case ARM::VST4q32:
- case ARM::VST4q8_UPD:
- case ARM::VST4q16_UPD:
- case ARM::VST4q32_UPD:
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- default:
- break;
+ case ARM::VST4d8:
+ case ARM::VST4d16:
+ case ARM::VST4d32:
+ case ARM::VST4d8_UPD:
+ case ARM::VST4d16_UPD:
+ case ARM::VST4d32_UPD:
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ case ARM::VST4q8:
+ case ARM::VST4q16:
+ case ARM::VST4q32:
+ case ARM::VST4q8_UPD:
+ case ARM::VST4q16_UPD:
+ case ARM::VST4q32_UPD:
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ default:
+ break;
}
return S;
@@ -3575,10 +2581,15 @@ static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
align *= (1 << size);
switch (Inst.getOpcode()) {
- case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
- case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
- case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
- case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
+ case ARM::VLD1DUPq16:
+ case ARM::VLD1DUPq32:
+ case ARM::VLD1DUPq8:
+ case ARM::VLD1DUPq16wb_fixed:
+ case ARM::VLD1DUPq16wb_register:
+ case ARM::VLD1DUPq32wb_fixed:
+ case ARM::VLD1DUPq32wb_register:
+ case ARM::VLD1DUPq8wb_fixed:
+ case ARM::VLD1DUPq8wb_register:
if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
break;
@@ -3617,20 +2628,30 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
unsigned Rm = fieldFromInstruction(Insn, 0, 4);
unsigned align = fieldFromInstruction(Insn, 4, 1);
unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
- align *= 2*size;
+ align *= 2 * size;
switch (Inst.getOpcode()) {
- case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
- case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
- case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
- case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
+ case ARM::VLD2DUPd16:
+ case ARM::VLD2DUPd32:
+ case ARM::VLD2DUPd8:
+ case ARM::VLD2DUPd16wb_fixed:
+ case ARM::VLD2DUPd16wb_register:
+ case ARM::VLD2DUPd32wb_fixed:
+ case ARM::VLD2DUPd32wb_register:
+ case ARM::VLD2DUPd8wb_fixed:
+ case ARM::VLD2DUPd8wb_register:
if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
break;
- case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
- case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
- case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
- case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
+ case ARM::VLD2DUPd16x2:
+ case ARM::VLD2DUPd32x2:
+ case ARM::VLD2DUPd8x2:
+ case ARM::VLD2DUPd16x2wb_fixed:
+ case ARM::VLD2DUPd16x2wb_register:
+ case ARM::VLD2DUPd32x2wb_fixed:
+ case ARM::VLD2DUPd32x2wb_register:
+ case ARM::VLD2DUPd8x2wb_fixed:
+ case ARM::VLD2DUPd8x2wb_register:
if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
break;
@@ -3668,9 +2689,11 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address,
+ Decoder)))
return MCDisassembler::Fail;
if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
@@ -3713,17 +2736,20 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
align *= 8;
} else {
size = 1 << size;
- align *= 4*size;
+ align *= 4 * size;
}
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
+ if (!Check(S,
+ DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address,
+ Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd + 3 * inc) % 32, Address,
+ Decoder)))
return MCDisassembler::Fail;
if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
@@ -3760,31 +2786,31 @@ static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
if (Q) {
if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
+ return MCDisassembler::Fail;
} else {
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
+ return MCDisassembler::Fail;
}
Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) {
- case ARM::VORRiv4i16:
- case ARM::VORRiv2i32:
- case ARM::VBICiv4i16:
- case ARM::VBICiv2i32:
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- case ARM::VORRiv8i16:
- case ARM::VORRiv4i32:
- case ARM::VBICiv8i16:
- case ARM::VBICiv4i32:
- if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- default:
- break;
+ case ARM::VORRiv4i16:
+ case ARM::VORRiv2i32:
+ case ARM::VBICiv4i16:
+ case ARM::VBICiv2i32:
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ case ARM::VORRiv8i16:
+ case ARM::VORRiv4i32:
+ case ARM::VBICiv8i16:
+ case ARM::VBICiv4i32:
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ default:
+ break;
}
return S;
@@ -3801,8 +2827,8 @@ static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
unsigned imm = fieldFromInstruction(Insn, 0, 4);
imm |= fieldFromInstruction(Insn, 16, 3) << 4;
imm |= fieldFromInstruction(Insn, 28, 1) << 7;
- imm |= cmode << 8;
- imm |= fieldFromInstruction(Insn, 5, 1) << 12;
+ imm |= cmode << 8;
+ imm |= fieldFromInstruction(Insn, 5, 1) << 12;
if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
return MCDisassembler::Fail;
@@ -3910,7 +2936,7 @@ static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (op) {
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail; // Writeback
+ return MCDisassembler::Fail; // Writeback
}
switch (Inst.getOpcode()) {
@@ -3941,14 +2967,14 @@ static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
return MCDisassembler::Fail;
- switch(Inst.getOpcode()) {
- default:
- return MCDisassembler::Fail;
- case ARM::tADR:
- break; // tADR does not explicitly represent the PC as an operand.
- case ARM::tADDrSPi:
- Inst.addOperand(MCOperand::createReg(ARM::SP));
- break;
+ switch (Inst.getOpcode()) {
+ default:
+ return MCDisassembler::Fail;
+ case ARM::tADR:
+ break; // tADR does not explicitly represent the PC as an operand.
+ case ARM::tADDrSPi:
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ break;
}
Inst.addOperand(MCOperand::createImm(imm));
@@ -3958,8 +2984,9 @@ static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
- if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
- true, 2, Inst, Decoder))
+ if (!tryAddingSymbolicOperand(Address,
+ Address + SignExtend32<12>(Val << 1) + 4, true,
+ 2, Inst, Decoder))
Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
return MCDisassembler::Success;
}
@@ -3976,8 +3003,8 @@ static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
- if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
- true, 2, Inst, Decoder))
+ if (!tryAddingSymbolicOperand(Address, Address + (Val << 1) + 4, true, 2,
+ Inst, Decoder))
Inst.addOperand(MCOperand::createImm(Val << 1));
return MCDisassembler::Success;
}
@@ -4063,6 +3090,60 @@ static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
return S;
}
+static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rt = fieldFromInstruction(Insn, 12, 4);
+ unsigned U = fieldFromInstruction(Insn, 23, 1);
+ int imm = fieldFromInstruction(Insn, 0, 12);
+
+ const FeatureBitset &featureBits =
+ Decoder->getSubtargetInfo().getFeatureBits();
+
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
+
+ if (Rt == 15) {
+ switch (Inst.getOpcode()) {
+ case ARM::t2LDRBpci:
+ case ARM::t2LDRHpci:
+ Inst.setOpcode(ARM::t2PLDpci);
+ break;
+ case ARM::t2LDRSBpci:
+ Inst.setOpcode(ARM::t2PLIpci);
+ break;
+ case ARM::t2LDRSHpci:
+ return MCDisassembler::Fail;
+ default:
+ break;
+ }
+ }
+
+ switch (Inst.getOpcode()) {
+ case ARM::t2PLDpci:
+ break;
+ case ARM::t2PLIpci:
+ if (!hasV7Ops)
+ return MCDisassembler::Fail;
+ break;
+ default:
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+
+ if (!U) {
+ // Special case for #-0.
+ if (imm == 0)
+ imm = INT32_MIN;
+ else
+ imm = -imm;
+ }
+ Inst.addOperand(MCOperand::createImm(imm));
+
+ return S;
+}
+
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -4123,19 +3204,19 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
}
switch (Inst.getOpcode()) {
- case ARM::t2PLDs:
- break;
- case ARM::t2PLIs:
- if (!hasV7Ops)
- return MCDisassembler::Fail;
- break;
- case ARM::t2PLDWs:
- if (!hasV7Ops || !hasMP)
- return MCDisassembler::Fail;
- break;
- default:
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
+ case ARM::t2PLDs:
+ break;
+ case ARM::t2PLIs:
+ if (!hasV7Ops)
+ return MCDisassembler::Fail;
+ break;
+ case ARM::t2PLDWs:
+ if (!hasV7Ops || !hasMP)
+ return MCDisassembler::Fail;
+ break;
+ default:
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
}
unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
@@ -4219,9 +3300,9 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
break;
case ARM::t2PLDWi8:
- if (!hasV7Ops || !hasMP)
- return MCDisassembler::Fail;
- break;
+ if (!hasV7Ops || !hasMP)
+ return MCDisassembler::Fail;
+ break;
default:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
@@ -4300,9 +3381,9 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
break;
case ARM::t2PLDWi12:
- if (!hasV7Ops || !hasMP)
- return MCDisassembler::Fail;
- break;
+ if (!hasV7Ops || !hasMP)
+ return MCDisassembler::Fail;
+ break;
default:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
@@ -4352,60 +3433,6 @@ static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
-static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
-
- unsigned Rt = fieldFromInstruction(Insn, 12, 4);
- unsigned U = fieldFromInstruction(Insn, 23, 1);
- int imm = fieldFromInstruction(Insn, 0, 12);
-
- const FeatureBitset &featureBits =
- Decoder->getSubtargetInfo().getFeatureBits();
-
- bool hasV7Ops = featureBits[ARM::HasV7Ops];
-
- if (Rt == 15) {
- switch (Inst.getOpcode()) {
- case ARM::t2LDRBpci:
- case ARM::t2LDRHpci:
- Inst.setOpcode(ARM::t2PLDpci);
- break;
- case ARM::t2LDRSBpci:
- Inst.setOpcode(ARM::t2PLIpci);
- break;
- case ARM::t2LDRSHpci:
- return MCDisassembler::Fail;
- default:
- break;
- }
- }
-
- switch(Inst.getOpcode()) {
- case ARM::t2PLDpci:
- break;
- case ARM::t2PLIpci:
- if (!hasV7Ops)
- return MCDisassembler::Fail;
- break;
- default:
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- }
-
- if (!U) {
- // Special case for #-0.
- if (imm == 0)
- imm = INT32_MIN;
- else
- imm = -imm;
- }
- Inst.addOperand(MCOperand::createImm(imm));
-
- return S;
-}
-
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
const MCDisassembler *Decoder) {
if (Val == 0)
@@ -4413,7 +3440,8 @@ static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
else {
int imm = Val & 0xFF;
- if (!(Val & 0x100)) imm *= -1;
+ if (!(Val & 0x100))
+ imm *= -1;
Inst.addOperand(MCOperand::createImm(imm * 4));
}
@@ -4535,18 +3563,18 @@ static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
// Some instructions always use an additive offset.
switch (Inst.getOpcode()) {
- case ARM::t2LDRT:
- case ARM::t2LDRBT:
- case ARM::t2LDRHT:
- case ARM::t2LDRSBT:
- case ARM::t2LDRSHT:
- case ARM::t2STRT:
- case ARM::t2STRBT:
- case ARM::t2STRHT:
- imm |= 0x100;
- break;
- default:
- break;
+ case ARM::t2LDRT:
+ case ARM::t2LDRBT:
+ case ARM::t2LDRHT:
+ case ARM::t2LDRSBT:
+ case ARM::t2LDRSHT:
+ case ARM::t2STRT:
+ case ARM::t2STRBT:
+ case ARM::t2STRHT:
+ imm |= 0x100;
+ break;
+ default:
+ break;
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
@@ -4704,17 +3732,17 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
- return MCDisassembler::Fail;
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
- return MCDisassembler::Fail;
+ return MCDisassembler::Fail;
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Inst.addOperand(MCOperand::createReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
- return MCDisassembler::Fail;
+ return MCDisassembler::Fail;
}
return S;
@@ -4772,9 +3800,9 @@ static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
return MCDisassembler::Fail;
- if(!fieldFromInstruction(Insn, 7, 1)) {
+ if (!fieldFromInstruction(Insn, 7, 1)) {
if (imm == 0)
- imm = INT32_MIN; // indicate -0
+ imm = INT32_MIN; // indicate -0
else
imm *= -1;
}
@@ -4803,9 +3831,8 @@ static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
int imm32 = SignExtend32<25>(tmp << 1);
- if (!tryAddingSymbolicOperand(Address,
- (Address & ~2u) + imm32 + 4,
- true, 4, Inst, Decoder))
+ if (!tryAddingSymbolicOperand(Address, (Address & ~2u) + imm32 + 4, true, 4,
+ Inst, Decoder))
Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
@@ -4836,12 +3863,23 @@ static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4);
- if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
+ if (Rn == 13 && !FeatureBits[ARM::HasV8Ops])
+ S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- return S;
+ return S;
+}
+
+static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if (Val & ~0xf)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createImm(Val));
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
@@ -4853,17 +3891,17 @@ static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
if (pred == 0xE || pred == 0xF) {
unsigned opc = fieldFromInstruction(Insn, 4, 28);
switch (opc) {
- default:
- return MCDisassembler::Fail;
- case 0xf3bf8f4:
- Inst.setOpcode(ARM::t2DSB);
- break;
- case 0xf3bf8f5:
- Inst.setOpcode(ARM::t2DMB);
- break;
- case 0xf3bf8f6:
- Inst.setOpcode(ARM::t2ISB);
- break;
+ default:
+ return MCDisassembler::Fail;
+ case 0xf3bf8f4:
+ Inst.setOpcode(ARM::t2DSB);
+ break;
+ case 0xf3bf8f5:
+ Inst.setOpcode(ARM::t2DMB);
+ break;
+ case 0xf3bf8f6:
+ Inst.setOpcode(ARM::t2ISB);
+ break;
}
unsigned imm = fieldFromInstruction(Insn, 0, 4);
@@ -4894,19 +3932,19 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
unsigned byte = fieldFromInstruction(Val, 8, 2);
unsigned imm = fieldFromInstruction(Val, 0, 8);
switch (byte) {
- case 0:
- Inst.addOperand(MCOperand::createImm(imm));
- break;
- case 1:
- Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
- break;
- case 2:
- Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
- break;
- case 3:
- Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
- (imm << 8) | imm));
- break;
+ case 0:
+ Inst.addOperand(MCOperand::createImm(imm));
+ break;
+ case 1:
+ Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
+ break;
+ case 2:
+ Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
+ break;
+ case 3:
+ Inst.addOperand(
+ MCOperand::createImm((imm << 24) | (imm << 16) | (imm << 8) | imm));
+ break;
}
} else {
unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
@@ -4921,8 +3959,9 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
- if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
- true, 2, Inst, Decoder))
+ if (!tryAddingSymbolicOperand(Address,
+ Address + SignExtend32<9>(Val << 1) + 4, true,
+ 2, Inst, Decoder))
Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
return MCDisassembler::Success;
}
@@ -4945,22 +3984,12 @@ static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
int imm32 = SignExtend32<25>(tmp << 1);
- if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
- true, 4, Inst, Decoder))
+ if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4, Inst,
+ Decoder))
Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
-static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (Val & ~0xf)
- return MCDisassembler::Fail;
-
- Inst.addOperand(MCOperand::createImm(Val));
- return MCDisassembler::Success;
-}
-
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -4982,15 +4011,15 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
// Validate the SYSm value first.
switch (ValLow) {
- case 0: // apsr
- case 1: // iapsr
- case 2: // eapsr
- case 3: // xpsr
- case 5: // ipsr
- case 6: // epsr
- case 7: // iepsr
- case 8: // msp
- case 9: // psp
+ case 0: // apsr
+ case 1: // iapsr
+ case 2: // eapsr
+ case 3: // xpsr
+ case 5: // ipsr
+ case 6: // epsr
+ case 7: // iepsr
+ case 8: // msp
+ case 9: // psp
case 16: // primask
case 20: // control
break;
@@ -5050,8 +4079,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
// unpredictable.
if (Mask != 2)
S = MCDisassembler::SoftFail;
- }
- else {
+ } else {
// The ARMv7-M architecture stores an additional 2-bit mask value in
// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
@@ -5123,7 +4151,7 @@ static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
+ if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1)
S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
@@ -5148,7 +4176,8 @@ static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
imm |= fieldFromInstruction(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction(Insn, 28, 4);
- if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
+ if (Rn == 0xF || Rn == Rt)
+ S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
@@ -5175,8 +4204,10 @@ static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
unsigned pred = fieldFromInstruction(Insn, 28, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4);
- if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
- if (Rm == 0xF) S = MCDisassembler::SoftFail;
+ if (Rn == 0xF || Rn == Rt)
+ S = MCDisassembler::SoftFail;
+ if (Rm == 0xF)
+ S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
@@ -5202,7 +4233,8 @@ static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
imm |= fieldFromInstruction(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction(Insn, 28, 4);
- if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
+ if (Rn == 0xF || Rn == Rt)
+ S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -5228,7 +4260,8 @@ static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
imm |= fieldFromInstruction(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction(Insn, 28, 4);
- if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
+ if (Rn == 0xF || Rn == Rt)
+ S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -5255,38 +4288,303 @@ static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
unsigned align = 0;
unsigned index = 0;
switch (size) {
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ if (fieldFromInstruction(Insn, 4, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 5, 3);
+ break;
+ case 1:
+ if (fieldFromInstruction(Insn, 5, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 2;
+ break;
+ case 2:
+ if (fieldFromInstruction(Insn, 6, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 7, 1);
+
+ switch (fieldFromInstruction(Insn, 4, 2)) {
+ case 0:
+ align = 0;
+ break;
+ case 3:
+ align = 4;
+ break;
default:
return MCDisassembler::Fail;
+ }
+ break;
+ }
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (Rm != 0xF) { // Writeback
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(align));
+ if (Rm != 0xF) {
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
+ Inst.addOperand(MCOperand::createReg(0));
+ }
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(index));
+
+ return S;
+}
+
+static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction(Insn, 0, 4);
+ unsigned Rd = fieldFromInstruction(Insn, 12, 4);
+ Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
+ unsigned size = fieldFromInstruction(Insn, 10, 2);
+
+ unsigned align = 0;
+ unsigned index = 0;
+ switch (size) {
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ if (fieldFromInstruction(Insn, 4, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 5, 3);
+ break;
+ case 1:
+ if (fieldFromInstruction(Insn, 5, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 2;
+ break;
+ case 2:
+ if (fieldFromInstruction(Insn, 6, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 7, 1);
+
+ switch (fieldFromInstruction(Insn, 4, 2)) {
case 0:
- if (fieldFromInstruction(Insn, 4, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 5, 3);
+ align = 0;
break;
- case 1:
- if (fieldFromInstruction(Insn, 5, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 4, 1))
- align = 2;
- break;
- case 2:
- if (fieldFromInstruction(Insn, 6, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 7, 1);
-
- switch (fieldFromInstruction(Insn, 4, 2)) {
- case 0 :
- align = 0; break;
- case 3:
- align = 4; break;
- default:
- return MCDisassembler::Fail;
- }
+ case 3:
+ align = 4;
break;
+ default:
+ return MCDisassembler::Fail;
+ }
+ break;
+ }
+
+ if (Rm != 0xF) { // Writeback
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(align));
+ if (Rm != 0xF) {
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
+ Inst.addOperand(MCOperand::createReg(0));
+ }
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(index));
+
+ return S;
+}
+
+static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction(Insn, 0, 4);
+ unsigned Rd = fieldFromInstruction(Insn, 12, 4);
+ Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
+ unsigned size = fieldFromInstruction(Insn, 10, 2);
+
+ unsigned align = 0;
+ unsigned index = 0;
+ unsigned inc = 1;
+ switch (size) {
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ index = fieldFromInstruction(Insn, 5, 3);
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 2;
+ break;
+ case 1:
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 4;
+ if (fieldFromInstruction(Insn, 5, 1))
+ inc = 2;
+ break;
+ case 2:
+ if (fieldFromInstruction(Insn, 5, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 7, 1);
+ if (fieldFromInstruction(Insn, 4, 1) != 0)
+ align = 8;
+ if (fieldFromInstruction(Insn, 6, 1))
+ inc = 2;
+ break;
+ }
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (Rm != 0xF) { // Writeback
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(align));
+ if (Rm != 0xF) {
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
+ Inst.addOperand(MCOperand::createReg(0));
+ }
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(index));
+
+ return S;
+}
+
+static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction(Insn, 0, 4);
+ unsigned Rd = fieldFromInstruction(Insn, 12, 4);
+ Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
+ unsigned size = fieldFromInstruction(Insn, 10, 2);
+
+ unsigned align = 0;
+ unsigned index = 0;
+ unsigned inc = 1;
+ switch (size) {
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ index = fieldFromInstruction(Insn, 5, 3);
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 2;
+ break;
+ case 1:
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 4;
+ if (fieldFromInstruction(Insn, 5, 1))
+ inc = 2;
+ break;
+ case 2:
+ if (fieldFromInstruction(Insn, 5, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 7, 1);
+ if (fieldFromInstruction(Insn, 4, 1) != 0)
+ align = 8;
+ if (fieldFromInstruction(Insn, 6, 1))
+ inc = 2;
+ break;
+ }
+
+ if (Rm != 0xF) { // Writeback
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(align));
+ if (Rm != 0xF) {
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
+ Inst.addOperand(MCOperand::createReg(0));
+ }
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(index));
+
+ return S;
+}
+
+static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction(Insn, 0, 4);
+ unsigned Rd = fieldFromInstruction(Insn, 12, 4);
+ Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
+ unsigned size = fieldFromInstruction(Insn, 10, 2);
+
+ unsigned align = 0;
+ unsigned index = 0;
+ unsigned inc = 1;
+ switch (size) {
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ if (fieldFromInstruction(Insn, 4, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 5, 3);
+ break;
+ case 1:
+ if (fieldFromInstruction(Insn, 4, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 5, 1))
+ inc = 2;
+ break;
+ case 2:
+ if (fieldFromInstruction(Insn, 4, 2))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 7, 1);
+ if (fieldFromInstruction(Insn, 6, 1))
+ inc = 2;
+ break;
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+
if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -5304,12 +4602,16 @@ static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index));
return S;
}
-static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
@@ -5321,40 +4623,34 @@ static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
unsigned align = 0;
unsigned index = 0;
+ unsigned inc = 1;
switch (size) {
- default:
- return MCDisassembler::Fail;
- case 0:
- if (fieldFromInstruction(Insn, 4, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 5, 3);
- break;
- case 1:
- if (fieldFromInstruction(Insn, 5, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 4, 1))
- align = 2;
- break;
- case 2:
- if (fieldFromInstruction(Insn, 6, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 7, 1);
-
- switch (fieldFromInstruction(Insn, 4, 2)) {
- case 0:
- align = 0; break;
- case 3:
- align = 4; break;
- default:
- return MCDisassembler::Fail;
- }
- break;
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ if (fieldFromInstruction(Insn, 4, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 5, 3);
+ break;
+ case 1:
+ if (fieldFromInstruction(Insn, 4, 1))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 5, 1))
+ inc = 2;
+ break;
+ case 2:
+ if (fieldFromInstruction(Insn, 4, 2))
+ return MCDisassembler::Fail; // UNDEFINED
+ index = fieldFromInstruction(Insn, 7, 1);
+ if (fieldFromInstruction(Insn, 6, 1))
+ inc = 2;
+ break;
}
if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
+ return MCDisassembler::Fail;
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -5362,19 +4658,23 @@ static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
- return MCDisassembler::Fail;
+ return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index));
return S;
}
-static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
@@ -5388,35 +4688,47 @@ static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
unsigned index = 0;
unsigned inc = 1;
switch (size) {
- default:
- return MCDisassembler::Fail;
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 4;
+ index = fieldFromInstruction(Insn, 5, 3);
+ break;
+ case 1:
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 8;
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 5, 1))
+ inc = 2;
+ break;
+ case 2:
+ switch (fieldFromInstruction(Insn, 4, 2)) {
case 0:
- index = fieldFromInstruction(Insn, 5, 3);
- if (fieldFromInstruction(Insn, 4, 1))
- align = 2;
+ align = 0;
break;
- case 1:
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 4, 1))
- align = 4;
- if (fieldFromInstruction(Insn, 5, 1))
- inc = 2;
- break;
- case 2:
- if (fieldFromInstruction(Insn, 5, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 7, 1);
- if (fieldFromInstruction(Insn, 4, 1) != 0)
- align = 8;
- if (fieldFromInstruction(Insn, 6, 1))
- inc = 2;
+ case 3:
+ return MCDisassembler::Fail;
+ default:
+ align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
+ }
+
+ index = fieldFromInstruction(Insn, 7, 1);
+ if (fieldFromInstruction(Insn, 6, 1))
+ inc = 2;
+ break;
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+
if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -5434,14 +4746,18 @@ static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index));
return S;
}
-static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
+static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
@@ -5455,29 +4771,36 @@ static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
unsigned index = 0;
unsigned inc = 1;
switch (size) {
- default:
- return MCDisassembler::Fail;
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 4;
+ index = fieldFromInstruction(Insn, 5, 3);
+ break;
+ case 1:
+ if (fieldFromInstruction(Insn, 4, 1))
+ align = 8;
+ index = fieldFromInstruction(Insn, 6, 2);
+ if (fieldFromInstruction(Insn, 5, 1))
+ inc = 2;
+ break;
+ case 2:
+ switch (fieldFromInstruction(Insn, 4, 2)) {
case 0:
- index = fieldFromInstruction(Insn, 5, 3);
- if (fieldFromInstruction(Insn, 4, 1))
- align = 2;
- break;
- case 1:
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 4, 1))
- align = 4;
- if (fieldFromInstruction(Insn, 5, 1))
- inc = 2;
+ align = 0;
break;
- case 2:
- if (fieldFromInstruction(Insn, 5, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 7, 1);
- if (fieldFromInstruction(Insn, 4, 1) != 0)
- align = 8;
- if (fieldFromInstruction(Insn, 6, 1))
- inc = 2;
+ case 3:
+ return MCDisassembler::Fail;
+ default:
+ align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
+ }
+
+ index = fieldFromInstruction(Insn, 7, 1);
+ if (fieldFromInstruction(Insn, 6, 1))
+ inc = 2;
+ break;
}
if (Rm != 0xF) { // Writeback
@@ -5497,1575 +4820,1805 @@ static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index));
return S;
}
-static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
+ unsigned Rt = fieldFromInstruction(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction(Insn, 5, 1);
+ unsigned pred = fieldFromInstruction(Insn, 28, 4);
+ Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction(Insn, 0, 4);
- unsigned Rd = fieldFromInstruction(Insn, 12, 4);
- Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction(Insn, 10, 2);
-
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
- switch (size) {
- default:
- return MCDisassembler::Fail;
- case 0:
- if (fieldFromInstruction(Insn, 4, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 5, 3);
- break;
- case 1:
- if (fieldFromInstruction(Insn, 4, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 5, 1))
- inc = 2;
- break;
- case 2:
- if (fieldFromInstruction(Insn, 4, 2))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 7, 1);
- if (fieldFromInstruction(Insn, 6, 1))
- inc = 2;
- break;
- }
+ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
+ S = MCDisassembler::SoftFail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
- if (Rm != 0xF) { // Writeback
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return S;
+}
+
+static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+ unsigned Rt = fieldFromInstruction(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction(Insn, 5, 1);
+ unsigned pred = fieldFromInstruction(Insn, 28, 4);
+ Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
+
+ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
+ S = MCDisassembler::SoftFail;
+
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
- }
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(align));
- if (Rm != 0xF) {
- if (Rm != 0xD) {
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- } else
- Inst.addOperand(MCOperand::createReg(0));
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
+
+static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+ unsigned pred = fieldFromInstruction(Insn, 4, 4);
+ unsigned mask = fieldFromInstruction(Insn, 0, 4);
+
+ if (pred == 0xF) {
+ pred = 0xE;
+ S = MCDisassembler::SoftFail;
}
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ if (mask == 0x0)
+ return MCDisassembler::Fail;
+
+ // IT masks are encoded as a sequence of replacement low-order bits
+ // for the condition code. So if the low bit of the starting
+ // condition code is 1, then we have to flip all the bits above the
+ // terminating bit (which is the lowest 1 bit).
+ if (pred & 1) {
+ unsigned LowBit = mask & -mask;
+ unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
+ mask ^= BitsAboveLowBit;
+ }
+
+ Inst.addOperand(MCOperand::createImm(pred));
+ Inst.addOperand(MCOperand::createImm(mask));
+ return S;
+}
+
+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rt = fieldFromInstruction(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ unsigned addr = fieldFromInstruction(Insn, 0, 8);
+ unsigned W = fieldFromInstruction(Insn, 21, 1);
+ unsigned U = fieldFromInstruction(Insn, 23, 1);
+ unsigned P = fieldFromInstruction(Insn, 24, 1);
+ bool writeback = (W == 1) | (P == 0);
+
+ addr |= (U << 8) | (Rn << 9);
+
+ if (writeback && (Rn == Rt || Rn == Rt2))
+ Check(S, MCDisassembler::SoftFail);
+ if (Rt == Rt2)
+ Check(S, MCDisassembler::SoftFail);
+
+ // Rt
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ // Rt2
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ // Writeback operand
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // addr
+ if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(index));
return S;
}
-static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
+ unsigned Rt = fieldFromInstruction(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction(Insn, 0, 4);
- unsigned Rd = fieldFromInstruction(Insn, 12, 4);
- Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction(Insn, 10, 2);
+ unsigned addr = fieldFromInstruction(Insn, 0, 8);
+ unsigned W = fieldFromInstruction(Insn, 21, 1);
+ unsigned U = fieldFromInstruction(Insn, 23, 1);
+ unsigned P = fieldFromInstruction(Insn, 24, 1);
+ bool writeback = (W == 1) | (P == 0);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
- switch (size) {
- default:
- return MCDisassembler::Fail;
- case 0:
- if (fieldFromInstruction(Insn, 4, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 5, 3);
- break;
- case 1:
- if (fieldFromInstruction(Insn, 4, 1))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 5, 1))
- inc = 2;
- break;
- case 2:
- if (fieldFromInstruction(Insn, 4, 2))
- return MCDisassembler::Fail; // UNDEFINED
- index = fieldFromInstruction(Insn, 7, 1);
- if (fieldFromInstruction(Insn, 6, 1))
- inc = 2;
- break;
- }
+ addr |= (U << 8) | (Rn << 9);
- if (Rm != 0xF) { // Writeback
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- }
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ if (writeback && (Rn == Rt || Rn == Rt2))
+ Check(S, MCDisassembler::SoftFail);
+
+ // Writeback operand
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(align));
- if (Rm != 0xF) {
- if (Rm != 0xD) {
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ // Rt
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
- } else
- Inst.addOperand(MCOperand::createReg(0));
- }
-
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ // Rt2
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ // addr
+ if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+
+ return S;
+}
+
+static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
+ unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
+ if (sign1 != sign2)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(index));
+ const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
+ assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
+ DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
+ unsigned Val = fieldFromInstruction(Insn, 0, 8);
+ Val |= fieldFromInstruction(Insn, 12, 3) << 8;
+ Val |= fieldFromInstruction(Insn, 26, 1) << 11;
+ // If sign, then it is decreasing the address.
+ if (sign1) {
+ // Following ARMv7 Architecture Manual, when the offset
+ // is zero, it is decoded as a subw, not as a adr.w
+ if (!Val) {
+ Inst.setOpcode(ARM::t2SUBri12);
+ Inst.addOperand(MCOperand::createReg(ARM::PC));
+ } else
+ Val = -Val;
+ }
+ Inst.addOperand(MCOperand::createImm(Val));
return S;
}
-static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
+ // Shift of "asr #32" is not allowed in Thumb2 mode.
+ if (Val == 0x20)
+ S = MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(Val));
+ return S;
+}
+
+static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ unsigned Rt = fieldFromInstruction(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction(Insn, 0, 4);
- unsigned Rd = fieldFromInstruction(Insn, 12, 4);
- Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction(Insn, 10, 2);
+ unsigned pred = fieldFromInstruction(Insn, 28, 4);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
- switch (size) {
- default:
- return MCDisassembler::Fail;
- case 0:
- if (fieldFromInstruction(Insn, 4, 1))
- align = 4;
- index = fieldFromInstruction(Insn, 5, 3);
- break;
- case 1:
- if (fieldFromInstruction(Insn, 4, 1))
- align = 8;
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 5, 1))
- inc = 2;
- break;
- case 2:
- switch (fieldFromInstruction(Insn, 4, 2)) {
- case 0:
- align = 0; break;
- case 3:
- return MCDisassembler::Fail;
- default:
- align = 4 << fieldFromInstruction(Insn, 4, 2); break;
- }
+ if (pred == 0xF)
+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
- index = fieldFromInstruction(Insn, 7, 1);
- if (fieldFromInstruction(Insn, 6, 1))
- inc = 2;
- break;
- }
+ DecodeStatus S = MCDisassembler::Success;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ if (Rt == Rn || Rn == Rt2)
+ S = MCDisassembler::SoftFail;
+
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
- if (Rm != 0xF) { // Writeback
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- }
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(align));
- if (Rm != 0xF) {
- if (Rm != 0xD) {
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return S;
+}
+
+static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ const FeatureBitset &featureBits =
+ Decoder->getSubtargetInfo().getFeatureBits();
+ bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
+
+ unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
+ Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
+ unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
+ Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
+ unsigned imm = fieldFromInstruction(Insn, 16, 6);
+ unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+ unsigned op = fieldFromInstruction(Insn, 5, 1);
+
+ DecodeStatus S = MCDisassembler::Success;
+
+ // If the top 3 bits of imm are clear, this is a VMOV (immediate)
+ if (!(imm & 0x38)) {
+ if (cmode == 0xF) {
+ if (op == 1)
return MCDisassembler::Fail;
- } else
- Inst.addOperand(MCOperand::createReg(0));
+ Inst.setOpcode(ARM::VMOVv2f32);
+ }
+ if (hasFullFP16) {
+ if (cmode == 0xE) {
+ if (op == 1) {
+ Inst.setOpcode(ARM::VMOVv1i64);
+ } else {
+ Inst.setOpcode(ARM::VMOVv8i8);
+ }
+ }
+ if (cmode == 0xD) {
+ if (op == 1) {
+ Inst.setOpcode(ARM::VMVNv2i32);
+ } else {
+ Inst.setOpcode(ARM::VMOVv2i32);
+ }
+ }
+ if (cmode == 0xC) {
+ if (op == 1) {
+ Inst.setOpcode(ARM::VMVNv2i32);
+ } else {
+ Inst.setOpcode(ARM::VMOVv2i32);
+ }
+ }
+ }
+ return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
}
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ if (!(imm & 0x20))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(index));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
-static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
+static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ const FeatureBitset &featureBits =
+ Decoder->getSubtargetInfo().getFeatureBits();
+ bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction(Insn, 0, 4);
- unsigned Rd = fieldFromInstruction(Insn, 12, 4);
- Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction(Insn, 10, 2);
+ unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
+ Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
+ unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
+ Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
+ unsigned imm = fieldFromInstruction(Insn, 16, 6);
+ unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+ unsigned op = fieldFromInstruction(Insn, 5, 1);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
- switch (size) {
- default:
- return MCDisassembler::Fail;
- case 0:
- if (fieldFromInstruction(Insn, 4, 1))
- align = 4;
- index = fieldFromInstruction(Insn, 5, 3);
- break;
- case 1:
- if (fieldFromInstruction(Insn, 4, 1))
- align = 8;
- index = fieldFromInstruction(Insn, 6, 2);
- if (fieldFromInstruction(Insn, 5, 1))
- inc = 2;
- break;
- case 2:
- switch (fieldFromInstruction(Insn, 4, 2)) {
- case 0:
- align = 0; break;
- case 3:
- return MCDisassembler::Fail;
- default:
- align = 4 << fieldFromInstruction(Insn, 4, 2); break;
- }
+ DecodeStatus S = MCDisassembler::Success;
- index = fieldFromInstruction(Insn, 7, 1);
- if (fieldFromInstruction(Insn, 6, 1))
- inc = 2;
- break;
+ // If the top 3 bits of imm are clear, this is a VMOV (immediate)
+ if (!(imm & 0x38)) {
+ if (cmode == 0xF) {
+ if (op == 1)
+ return MCDisassembler::Fail;
+ Inst.setOpcode(ARM::VMOVv4f32);
+ }
+ if (hasFullFP16) {
+ if (cmode == 0xE) {
+ if (op == 1) {
+ Inst.setOpcode(ARM::VMOVv2i64);
+ } else {
+ Inst.setOpcode(ARM::VMOVv16i8);
+ }
+ }
+ if (cmode == 0xD) {
+ if (op == 1) {
+ Inst.setOpcode(ARM::VMVNv4i32);
+ } else {
+ Inst.setOpcode(ARM::VMOVv4i32);
+ }
+ }
+ if (cmode == 0xC) {
+ if (op == 1) {
+ Inst.setOpcode(ARM::VMVNv4i32);
+ } else {
+ Inst.setOpcode(ARM::VMOVv4i32);
+ }
+ }
+ }
+ return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
}
- if (Rm != 0xF) { // Writeback
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ if (!(imm & 0x20))
return MCDisassembler::Fail;
- }
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(align));
- if (Rm != 0xF) {
- if (Rm != 0xD) {
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
- return MCDisassembler::Fail;
- } else
- Inst.addOperand(MCOperand::createReg(0));
- }
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(index));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
-static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus
+DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
+ Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
+ unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
+ Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
+ unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
+ Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
+ unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
+ unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
+
DecodeStatus S = MCDisassembler::Success;
- unsigned Rt = fieldFromInstruction(Insn, 12, 4);
- unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction(Insn, 5, 1);
- unsigned pred = fieldFromInstruction(Insn, 28, 4);
- Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
- if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
- S = MCDisassembler::SoftFail;
+ auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
- if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
+ if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
+ if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
+ if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
+ // The lane index does not have any bits in the encoding, because it can only
+ // be 0.
+ Inst.addOperand(MCOperand::createImm(0));
+ Inst.addOperand(MCOperand::createImm(rotate));
return S;
}
-static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- unsigned Rt = fieldFromInstruction(Insn, 12, 4);
- unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction(Insn, 5, 1);
- unsigned pred = fieldFromInstruction(Insn, 28, 4);
- Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
- if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
+ unsigned Rn = fieldFromInstruction(Val, 16, 4);
+ unsigned Rt = fieldFromInstruction(Val, 12, 4);
+ unsigned Rm = fieldFromInstruction(Val, 0, 4);
+ Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
+ unsigned Cond = fieldFromInstruction(Val, 28, 4);
+
+ if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
S = MCDisassembler::SoftFail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
+ if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
+ if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}
-static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- unsigned pred = fieldFromInstruction(Insn, 4, 4);
- unsigned mask = fieldFromInstruction(Insn, 0, 4);
- if (pred == 0xF) {
- pred = 0xE;
- S = MCDisassembler::SoftFail;
- }
+ unsigned CRm = fieldFromInstruction(Val, 0, 4);
+ unsigned opc1 = fieldFromInstruction(Val, 4, 4);
+ unsigned cop = fieldFromInstruction(Val, 8, 4);
+ unsigned Rt = fieldFromInstruction(Val, 12, 4);
+ unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
- if (mask == 0x0)
+ if ((cop & ~0x1) == 0xa)
return MCDisassembler::Fail;
- // IT masks are encoded as a sequence of replacement low-order bits
- // for the condition code. So if the low bit of the starting
- // condition code is 1, then we have to flip all the bits above the
- // terminating bit (which is the lowest 1 bit).
- if (pred & 1) {
- unsigned LowBit = mask & -mask;
- unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
- mask ^= BitsAboveLowBit;
+ if (Rt == Rt2)
+ S = MCDisassembler::SoftFail;
+
+ // We have to check if the instruction is MRRC2
+ // or MCRR2 when constructing the operands for
+ // Inst. Reason is because MRRC2 stores to two
+ // registers so it's tablegen desc has two
+ // outputs whereas MCRR doesn't store to any
+ // registers so all of it's operands are listed
+ // as inputs, therefore the operand order for
+ // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
+ // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
+
+ if (Inst.getOpcode() == ARM::MRRC2) {
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ Inst.addOperand(MCOperand::createImm(cop));
+ Inst.addOperand(MCOperand::createImm(opc1));
+ if (Inst.getOpcode() == ARM::MCRR2) {
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler::Fail;
}
+ Inst.addOperand(MCOperand::createImm(CRm));
- Inst.addOperand(MCOperand::createImm(pred));
- Inst.addOperand(MCOperand::createImm(mask));
return S;
}
-static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ const FeatureBitset &featureBits =
+ Decoder->getSubtargetInfo().getFeatureBits();
DecodeStatus S = MCDisassembler::Success;
- unsigned Rt = fieldFromInstruction(Insn, 12, 4);
- unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned addr = fieldFromInstruction(Insn, 0, 8);
- unsigned W = fieldFromInstruction(Insn, 21, 1);
- unsigned U = fieldFromInstruction(Insn, 23, 1);
- unsigned P = fieldFromInstruction(Insn, 24, 1);
- bool writeback = (W == 1) | (P == 0);
+ // Add explicit operand for the destination sysreg, for cases where
+ // we have to model it for code generation purposes.
+ switch (Inst.getOpcode()) {
+ case ARM::VMSR_FPSCR_NZCVQC:
+ Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+ break;
+ case ARM::VMSR_P0:
+ Inst.addOperand(MCOperand::createReg(ARM::VPR));
+ break;
+ }
- addr |= (U << 8) | (Rn << 9);
+ if (Inst.getOpcode() != ARM::FMSTAT) {
+ unsigned Rt = fieldFromInstruction(Val, 12, 4);
- if (writeback && (Rn == Rt || Rn == Rt2))
- Check(S, MCDisassembler::SoftFail);
- if (Rt == Rt2)
- Check(S, MCDisassembler::SoftFail);
+ if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
+ if (Rt == 13 || Rt == 15)
+ S = MCDisassembler::SoftFail;
+ Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ } else
+ Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
+ }
- // Rt
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- // Rt2
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
- return MCDisassembler::Fail;
- // Writeback operand
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- // addr
- if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
- return MCDisassembler::Fail;
+ // Add explicit operand for the source sysreg, similarly to above.
+ switch (Inst.getOpcode()) {
+ case ARM::VMRS_FPSCR_NZCVQC:
+ Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+ break;
+ case ARM::VMRS_P0:
+ Inst.addOperand(MCOperand::createReg(ARM::VPR));
+ break;
+ }
+
+ if (featureBits[ARM::ModeThumb]) {
+ Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+ Inst.addOperand(MCOperand::createReg(0));
+ } else {
+ unsigned pred = fieldFromInstruction(Val, 28, 4);
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
return S;
}
-static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
+static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
+ if (Val == 0 && !zeroPermitted)
+ S = MCDisassembler::Fail;
- unsigned Rt = fieldFromInstruction(Insn, 12, 4);
- unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned addr = fieldFromInstruction(Insn, 0, 8);
- unsigned W = fieldFromInstruction(Insn, 21, 1);
- unsigned U = fieldFromInstruction(Insn, 23, 1);
- unsigned P = fieldFromInstruction(Insn, 24, 1);
- bool writeback = (W == 1) | (P == 0);
+ uint64_t DecVal;
+ if (isSigned)
+ DecVal = SignExtend32<size + 1>(Val << 1);
+ else
+ DecVal = (Val << 1);
- addr |= (U << 8) | (Rn << 9);
+ if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
+ Decoder))
+ Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
+ return S;
+}
- if (writeback && (Rn == Rt || Rn == Rt2))
- Check(S, MCDisassembler::SoftFail);
+static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
- // Writeback operand
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- // Rt
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- // Rt2
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
- return MCDisassembler::Fail;
- // addr
- if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
- return MCDisassembler::Fail;
+ uint64_t LocImm = Inst.getOperand(0).getImm();
+ Val = LocImm + (2 << Val);
+ if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
+ Decoder))
+ Inst.addOperand(MCOperand::createImm(Val));
+ return MCDisassembler::Success;
+}
- return S;
+static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if (Val >= ARMCC::AL) // also exclude the non-condition NV
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::createImm(Val));
+ return MCDisassembler::Success;
}
-static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
- unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
- if (sign1 != sign2) return MCDisassembler::Fail;
- const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
- assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
- DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
+static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ if (Inst.getOpcode() == ARM::MVE_LCTP)
+ return S;
+
+ unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
+ fieldFromInstruction(Insn, 1, 10) << 1;
+ switch (Inst.getOpcode()) {
+ case ARM::t2LEUpdate:
+ case ARM::MVE_LETP:
+ Inst.addOperand(MCOperand::createReg(ARM::LR));
+ Inst.addOperand(MCOperand::createReg(ARM::LR));
+ [[fallthrough]];
+ case ARM::t2LE:
+ if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(
+ Inst, Imm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ case ARM::t2WLS:
+ case ARM::MVE_WLSTP_8:
+ case ARM::MVE_WLSTP_16:
+ case ARM::MVE_WLSTP_32:
+ case ARM::MVE_WLSTP_64:
+ Inst.addOperand(MCOperand::createReg(ARM::LR));
+ if (!Check(S,
+ DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
+ Address, Decoder)) ||
+ !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
+ Inst, Imm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
+ case ARM::t2DLS:
+ case ARM::MVE_DLSTP_8:
+ case ARM::MVE_DLSTP_16:
+ case ARM::MVE_DLSTP_32:
+ case ARM::MVE_DLSTP_64:
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ if (Rn == 0xF) {
+ // Enforce all the rest of the instruction bits in LCTP, which
+ // won't have been reliably checked based on LCTP's own tablegen
+ // record, because we came to this decode by a roundabout route.
+ uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
+ if ((Insn & ~SBZMask) != CanonicalLCTP)
+ return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
+ if (Insn != CanonicalLCTP)
+ Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
- unsigned Val = fieldFromInstruction(Insn, 0, 8);
- Val |= fieldFromInstruction(Insn, 12, 3) << 8;
- Val |= fieldFromInstruction(Insn, 26, 1) << 11;
- // If sign, then it is decreasing the address.
- if (sign1) {
- // Following ARMv7 Architecture Manual, when the offset
- // is zero, it is decoded as a subw, not as a adr.w
- if (!Val) {
- Inst.setOpcode(ARM::t2SUBri12);
- Inst.addOperand(MCOperand::createReg(ARM::PC));
- } else
- Val = -Val;
+ Inst.setOpcode(ARM::MVE_LCTP);
+ } else {
+ Inst.addOperand(MCOperand::createReg(ARM::LR));
+ if (!Check(S, DecoderGPRRegisterClass(Inst,
+ fieldFromInstruction(Insn, 16, 4),
+ Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ break;
}
- Inst.addOperand(MCOperand::createImm(Val));
return S;
}
-static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- // Shift of "asr #32" is not allowed in Thumb2 mode.
- if (Val == 0x20) S = MCDisassembler::Fail;
+ if (Val == 0)
+ Val = 32;
+
Inst.addOperand(MCOperand::createImm(Val));
+
return S;
}
-static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- unsigned Rt = fieldFromInstruction(Insn, 12, 4);
- unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- unsigned pred = fieldFromInstruction(Insn, 28, 4);
-
- if (pred == 0xF)
- return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
-
- DecodeStatus S = MCDisassembler::Success;
-
- if (Rt == Rn || Rn == Rt2)
- S = MCDisassembler::SoftFail;
-
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if ((RegNo) + 1 > 11)
return MCDisassembler::Fail;
- return S;
+ unsigned Register = GPRDecoderTable[(RegNo) + 1];
+ Inst.addOperand(MCOperand::createReg(Register));
+ return MCDisassembler::Success;
}
-static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- const FeatureBitset &featureBits =
- Decoder->getSubtargetInfo().getFeatureBits();
- bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
-
- unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
- Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
- unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
- Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
- unsigned imm = fieldFromInstruction(Insn, 16, 6);
- unsigned cmode = fieldFromInstruction(Insn, 8, 4);
- unsigned op = fieldFromInstruction(Insn, 5, 1);
-
- DecodeStatus S = MCDisassembler::Success;
-
- // If the top 3 bits of imm are clear, this is a VMOV (immediate)
- if (!(imm & 0x38)) {
- if (cmode == 0xF) {
- if (op == 1) return MCDisassembler::Fail;
- Inst.setOpcode(ARM::VMOVv2f32);
- }
- if (hasFullFP16) {
- if (cmode == 0xE) {
- if (op == 1) {
- Inst.setOpcode(ARM::VMOVv1i64);
- } else {
- Inst.setOpcode(ARM::VMOVv8i8);
- }
- }
- if (cmode == 0xD) {
- if (op == 1) {
- Inst.setOpcode(ARM::VMVNv2i32);
- } else {
- Inst.setOpcode(ARM::VMOVv2i32);
- }
- }
- if (cmode == 0xC) {
- if (op == 1) {
- Inst.setOpcode(ARM::VMVNv2i32);
- } else {
- Inst.setOpcode(ARM::VMOVv2i32);
- }
- }
- }
- return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
- }
-
- if (!(imm & 0x20)) return MCDisassembler::Fail;
-
- if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
+static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if ((RegNo) > 14)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(64 - imm));
- return S;
+ unsigned Register = GPRDecoderTable[(RegNo)];
+ Inst.addOperand(MCOperand::createReg(Register));
+ return MCDisassembler::Success;
}
-static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- const FeatureBitset &featureBits =
- Decoder->getSubtargetInfo().getFeatureBits();
- bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
-
- unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
- Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
- unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
- Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
- unsigned imm = fieldFromInstruction(Insn, 16, 6);
- unsigned cmode = fieldFromInstruction(Insn, 8, 4);
- unsigned op = fieldFromInstruction(Insn, 5, 1);
-
- DecodeStatus S = MCDisassembler::Success;
-
- // If the top 3 bits of imm are clear, this is a VMOV (immediate)
- if (!(imm & 0x38)) {
- if (cmode == 0xF) {
- if (op == 1) return MCDisassembler::Fail;
- Inst.setOpcode(ARM::VMOVv4f32);
- }
- if (hasFullFP16) {
- if (cmode == 0xE) {
- if (op == 1) {
- Inst.setOpcode(ARM::VMOVv2i64);
- } else {
- Inst.setOpcode(ARM::VMOVv16i8);
- }
- }
- if (cmode == 0xD) {
- if (op == 1) {
- Inst.setOpcode(ARM::VMVNv4i32);
- } else {
- Inst.setOpcode(ARM::VMOVv4i32);
- }
- }
- if (cmode == 0xC) {
- if (op == 1) {
- Inst.setOpcode(ARM::VMVNv4i32);
- } else {
- Inst.setOpcode(ARM::VMOVv4i32);
- }
- }
- }
- return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
+static DecodeStatus
+DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ if (RegNo == 15) {
+ Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
+ return MCDisassembler::Success;
}
- if (!(imm & 0x20)) return MCDisassembler::Fail;
+ unsigned Register = GPRDecoderTable[RegNo];
+ Inst.addOperand(MCOperand::createReg(Register));
- if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
- return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(64 - imm));
+ if (RegNo == 13)
+ return MCDisassembler::SoftFail;
- return S;
+ return MCDisassembler::Success;
}
-static DecodeStatus
-DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
- Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
- unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
- Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
- unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
- Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
- unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
- unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
-
+static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
-
- if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
- return MCDisassembler::Fail;
- // The lane index does not have any bits in the encoding, because it can only
- // be 0.
- Inst.addOperand(MCOperand::createImm(0));
- Inst.addOperand(MCOperand::createImm(rotate));
+ Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+ Inst.addOperand(MCOperand::createReg(0));
+ unsigned regs = fieldFromInstruction(Insn, 0, 8);
+ if (regs == 0) {
+ // Register list contains only VPR
+ } else if (Inst.getOpcode() == ARM::VSCCLRMD) {
+ unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) |
+ (fieldFromInstruction(Insn, 22, 1) << 12);
+ if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
+ return MCDisassembler::Fail;
+ }
+ } else {
+ unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) |
+ fieldFromInstruction(Insn, 22, 1);
+ // Registers past s31 are permitted and treated as being half of a d
+ // register, though both halves of each d register must be present.
+ unsigned max_reg = Vd + regs;
+ if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
+ S = MCDisassembler::SoftFail;
+ unsigned max_sreg = std::min(32u, max_reg);
+ unsigned max_dreg = std::min(32u, max_reg / 2);
+ for (unsigned i = Vd; i < max_sreg; ++i)
+ if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder)))
+ return MCDisassembler::Fail;
+ for (unsigned i = 16; i < max_dreg; ++i)
+ if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ Inst.addOperand(MCOperand::createReg(ARM::VPR));
return S;
}
-static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- unsigned Rn = fieldFromInstruction(Val, 16, 4);
- unsigned Rt = fieldFromInstruction(Val, 12, 4);
- unsigned Rm = fieldFromInstruction(Val, 0, 4);
- Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
- unsigned Cond = fieldFromInstruction(Val, 28, 4);
+ // Parse VPT mask and encode it in the MCInst as an immediate with the same
+ // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and
+ // 't' as 0 and finish with a 1.
+ unsigned Imm = 0;
+ // We always start with a 't'.
+ unsigned CurBit = 0;
+ for (int i = 3; i >= 0; --i) {
+ // If the bit we are looking at is not the same as last one, invert the
+ // CurBit, if it is the same leave it as is.
+ CurBit ^= (Val >> i) & 1U;
- if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
- S = MCDisassembler::SoftFail;
+ // Encode the CurBit at the right place in the immediate.
+ Imm |= (CurBit << i);
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
- return MCDisassembler::Fail;
+ // If we are done, finish the encoding with a 1.
+ if ((Val & ~(~0U << i)) == 0) {
+ Imm |= 1U << i;
+ break;
+ }
+ }
+
+ Inst.addOperand(MCOperand::createImm(Imm));
return S;
}
-static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
+static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ // The vpred_r operand type includes an MQPR register field derived
+ // from the encoding. But we don't actually want to add an operand
+ // to the MCInst at this stage, because AddThumbPredicate will do it
+ // later, and will infer the register number from the TIED_TO
+ // constraint. So this is a deliberately empty decoder method that
+ // will inhibit the auto-generated disassembly code from adding an
+ // operand at all.
+ return MCDisassembler::Success;
+}
- unsigned CRm = fieldFromInstruction(Val, 0, 4);
- unsigned opc1 = fieldFromInstruction(Val, 4, 4);
- unsigned cop = fieldFromInstruction(Val, 8, 4);
- unsigned Rt = fieldFromInstruction(Val, 12, 4);
- unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
+[[maybe_unused]] static DecodeStatus
+DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ // Similar to above, we want to ensure that no operands are added for the
+ // vpred operands. (This is marked "maybe_unused" for the moment; because
+ // DecoderEmitter currently (wrongly) omits operands with no instruction bits,
+ // the decoder doesn't actually call it yet. That will be addressed in a
+ // future change.)
+ return MCDisassembler::Success;
+}
- if ((cop & ~0x1) == 0xa)
- return MCDisassembler::Fail;
+static DecodeStatus
+DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(
+ MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
+ return MCDisassembler::Success;
+}
- if (Rt == Rt2)
- S = MCDisassembler::SoftFail;
+static DecodeStatus
+DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ unsigned Code;
+ switch (Val & 0x3) {
+ case 0:
+ Code = ARMCC::GE;
+ break;
+ case 1:
+ Code = ARMCC::LT;
+ break;
+ case 2:
+ Code = ARMCC::GT;
+ break;
+ case 3:
+ Code = ARMCC::LE;
+ break;
+ }
+ Inst.addOperand(MCOperand::createImm(Code));
+ return MCDisassembler::Success;
+}
- // We have to check if the instruction is MRRC2
- // or MCRR2 when constructing the operands for
- // Inst. Reason is because MRRC2 stores to two
- // registers so it's tablegen desc has two
- // outputs whereas MCRR doesn't store to any
- // registers so all of it's operands are listed
- // as inputs, therefore the operand order for
- // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
- // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
+static DecodeStatus
+DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(
+ MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
+ return MCDisassembler::Success;
+}
- if (Inst.getOpcode() == ARM::MRRC2) {
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
- return MCDisassembler::Fail;
- }
- Inst.addOperand(MCOperand::createImm(cop));
- Inst.addOperand(MCOperand::createImm(opc1));
- if (Inst.getOpcode() == ARM::MCRR2) {
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
- return MCDisassembler::Fail;
+static DecodeStatus
+DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ unsigned Code;
+ switch (Val) {
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ Code = ARMCC::EQ;
+ break;
+ case 1:
+ Code = ARMCC::NE;
+ break;
+ case 4:
+ Code = ARMCC::GE;
+ break;
+ case 5:
+ Code = ARMCC::LT;
+ break;
+ case 6:
+ Code = ARMCC::GT;
+ break;
+ case 7:
+ Code = ARMCC::LE;
+ break;
}
- Inst.addOperand(MCOperand::createImm(CRm));
- return S;
+ Inst.addOperand(MCOperand::createImm(Code));
+ return MCDisassembler::Success;
}
-static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address,
const MCDisassembler *Decoder) {
- const FeatureBitset &featureBits =
- Decoder->getSubtargetInfo().getFeatureBits();
DecodeStatus S = MCDisassembler::Success;
- // Add explicit operand for the destination sysreg, for cases where
- // we have to model it for code generation purposes.
+ unsigned DecodedVal = 64 - Val;
+
switch (Inst.getOpcode()) {
- case ARM::VMSR_FPSCR_NZCVQC:
- Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+ case ARM::MVE_VCVTf16s16_fix:
+ case ARM::MVE_VCVTs16f16_fix:
+ case ARM::MVE_VCVTf16u16_fix:
+ case ARM::MVE_VCVTu16f16_fix:
+ if (DecodedVal > 16)
+ return MCDisassembler::Fail;
break;
- case ARM::VMSR_P0:
- Inst.addOperand(MCOperand::createReg(ARM::VPR));
+ case ARM::MVE_VCVTf32s32_fix:
+ case ARM::MVE_VCVTs32f32_fix:
+ case ARM::MVE_VCVTf32u32_fix:
+ case ARM::MVE_VCVTu32f32_fix:
+ if (DecodedVal > 32)
+ return MCDisassembler::Fail;
break;
}
- if (Inst.getOpcode() != ARM::FMSTAT) {
- unsigned Rt = fieldFromInstruction(Val, 12, 4);
+ Inst.addOperand(MCOperand::createImm(64 - Val));
- if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
- if (Rt == 13 || Rt == 15)
- S = MCDisassembler::SoftFail;
- Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
- } else
- Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
+ return S;
+}
+
+static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
+ switch (Opcode) {
+ case ARM::VSTR_P0_off:
+ case ARM::VSTR_P0_pre:
+ case ARM::VSTR_P0_post:
+ case ARM::VLDR_P0_off:
+ case ARM::VLDR_P0_pre:
+ case ARM::VLDR_P0_post:
+ return ARM::P0;
+ case ARM::VSTR_FPSCR_NZCVQC_off:
+ case ARM::VSTR_FPSCR_NZCVQC_pre:
+ case ARM::VSTR_FPSCR_NZCVQC_post:
+ case ARM::VLDR_FPSCR_NZCVQC_off:
+ case ARM::VLDR_FPSCR_NZCVQC_pre:
+ case ARM::VLDR_FPSCR_NZCVQC_post:
+ return ARM::FPSCR;
+ default:
+ return 0;
}
+}
- // Add explicit operand for the source sysreg, similarly to above.
+template <bool Writeback>
+static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
switch (Inst.getOpcode()) {
- case ARM::VMRS_FPSCR_NZCVQC:
- Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
- break;
- case ARM::VMRS_P0:
- Inst.addOperand(MCOperand::createReg(ARM::VPR));
- break;
+ case ARM::VSTR_FPSCR_pre:
+ case ARM::VSTR_FPSCR_NZCVQC_pre:
+ case ARM::VLDR_FPSCR_pre:
+ case ARM::VLDR_FPSCR_NZCVQC_pre:
+ case ARM::VSTR_FPSCR_off:
+ case ARM::VSTR_FPSCR_NZCVQC_off:
+ case ARM::VLDR_FPSCR_off:
+ case ARM::VLDR_FPSCR_NZCVQC_off:
+ case ARM::VSTR_FPSCR_post:
+ case ARM::VSTR_FPSCR_NZCVQC_post:
+ case ARM::VLDR_FPSCR_post:
+ case ARM::VLDR_FPSCR_NZCVQC_post:
+ const FeatureBitset &featureBits =
+ Decoder->getSubtargetInfo().getFeatureBits();
+
+ if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
+ return MCDisassembler::Fail;
}
- if (featureBits[ARM::ModeThumb]) {
- Inst.addOperand(MCOperand::createImm(ARMCC::AL));
- Inst.addOperand(MCOperand::createReg(0));
- } else {
- unsigned pred = fieldFromInstruction(Val, 28, 4);
- if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ DecodeStatus S = MCDisassembler::Success;
+ if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
+ Inst.addOperand(MCOperand::createReg(Sysreg));
+ unsigned Rn = fieldFromInstruction(Val, 16, 4);
+ unsigned addr = fieldFromInstruction(Val, 0, 7) |
+ (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+
+ if (Writeback) {
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
}
+ if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+ Inst.addOperand(MCOperand::createReg(0));
return S;
}
-template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
-static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+static inline DecodeStatus
+DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
+ const MCDisassembler *Decoder, unsigned Rn,
+ OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
DecodeStatus S = MCDisassembler::Success;
- if (Val == 0 && !zeroPermitted)
- S = MCDisassembler::Fail;
- uint64_t DecVal;
- if (isSigned)
- DecVal = SignExtend32<size + 1>(Val << 1);
- else
- DecVal = (Val << 1);
+ unsigned Qd = fieldFromInstruction(Val, 13, 3);
+ unsigned addr = fieldFromInstruction(Val, 0, 7) |
+ (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+
+ if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
+ return MCDisassembler::Fail;
- if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
- Decoder))
- Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
return S;
}
-static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+template <int shift>
+static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
+ fieldFromInstruction(Val, 16, 3),
+ DecodetGPRRegisterClass, DecodeTAddrModeImm7<shift>);
+}
- uint64_t LocImm = Inst.getOperand(0).getImm();
- Val = LocImm + (2 << Val);
- if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
- Decoder))
- Inst.addOperand(MCOperand::createImm(Val));
- return MCDisassembler::Success;
+template <int shift>
+static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ return DecodeMVE_MEM_pre(
+ Inst, Val, Address, Decoder, fieldFromInstruction(Val, 16, 4),
+ DecoderGPRRegisterClass, DecodeT2AddrModeImm7<shift, 1>);
}
-static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (Val >= ARMCC::AL) // also exclude the non-condition NV
- return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::createImm(Val));
- return MCDisassembler::Success;
+template <int shift>
+static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
+ fieldFromInstruction(Val, 17, 3),
+ DecodeMQPRRegisterClass, DecodeMveAddrModeQ<shift>);
}
-static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
+template <unsigned MinLog, unsigned MaxLog>
+static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- if (Inst.getOpcode() == ARM::MVE_LCTP)
- return S;
-
- unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
- fieldFromInstruction(Insn, 1, 10) << 1;
- switch (Inst.getOpcode()) {
- case ARM::t2LEUpdate:
- case ARM::MVE_LETP:
- Inst.addOperand(MCOperand::createReg(ARM::LR));
- Inst.addOperand(MCOperand::createReg(ARM::LR));
- [[fallthrough]];
- case ARM::t2LE:
- if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(
- Inst, Imm, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- case ARM::t2WLS:
- case ARM::MVE_WLSTP_8:
- case ARM::MVE_WLSTP_16:
- case ARM::MVE_WLSTP_32:
- case ARM::MVE_WLSTP_64:
- Inst.addOperand(MCOperand::createReg(ARM::LR));
- if (!Check(S,
- DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
- Address, Decoder)) ||
- !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
- Inst, Imm, Address, Decoder)))
- return MCDisassembler::Fail;
- break;
- case ARM::t2DLS:
- case ARM::MVE_DLSTP_8:
- case ARM::MVE_DLSTP_16:
- case ARM::MVE_DLSTP_32:
- case ARM::MVE_DLSTP_64:
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- if (Rn == 0xF) {
- // Enforce all the rest of the instruction bits in LCTP, which
- // won't have been reliably checked based on LCTP's own tablegen
- // record, because we came to this decode by a roundabout route.
- uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
- if ((Insn & ~SBZMask) != CanonicalLCTP)
- return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
- if (Insn != CanonicalLCTP)
- Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
+ if (Val < MinLog || Val > MaxLog)
+ return MCDisassembler::Fail;
- Inst.setOpcode(ARM::MVE_LCTP);
- } else {
- Inst.addOperand(MCOperand::createReg(ARM::LR));
- if (!Check(S, DecoderGPRRegisterClass(Inst,
- fieldFromInstruction(Insn, 16, 4),
- Address, Decoder)))
- return MCDisassembler::Fail;
- }
- break;
- }
+ Inst.addOperand(MCOperand::createImm(1LL << Val));
return S;
}
-static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+template <unsigned start>
+static DecodeStatus
+DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- if (Val == 0)
- Val = 32;
-
- Inst.addOperand(MCOperand::createImm(Val));
+ Inst.addOperand(MCOperand::createImm(start + Val));
return S;
}
-static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if ((RegNo) + 1 > 11)
+static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+ unsigned Rt = fieldFromInstruction(Insn, 0, 4);
+ unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
+ unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+ fieldFromInstruction(Insn, 13, 3));
+ unsigned index = fieldFromInstruction(Insn, 4, 1);
+
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S,
+ DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S,
+ DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
return MCDisassembler::Fail;
- unsigned Register = GPRDecoderTable[(RegNo) + 1];
- Inst.addOperand(MCOperand::createReg(Register));
- return MCDisassembler::Success;
+ return S;
}
-static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if ((RegNo) > 14)
+static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+ unsigned Rt = fieldFromInstruction(Insn, 0, 4);
+ unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
+ unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+ fieldFromInstruction(Insn, 13, 3));
+ unsigned index = fieldFromInstruction(Insn, 4, 1);
+
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S,
+ DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S,
+ DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
return MCDisassembler::Fail;
- unsigned Register = GPRDecoderTable[(RegNo)];
- Inst.addOperand(MCOperand::createReg(Register));
- return MCDisassembler::Success;
+ return S;
}
static DecodeStatus
-DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (RegNo == 15) {
- Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
- return MCDisassembler::Success;
- }
-
- unsigned Register = GPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::createReg(Register));
-
- if (RegNo == 13)
- return MCDisassembler::SoftFail;
+DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
- return MCDisassembler::Success;
-}
+ unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
+ unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
+ unsigned Rm = fieldFromInstruction(Insn, 12, 4);
-static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
+ if (RdaHi == 14) {
+ // This value of RdaHi (really indicating pc, because RdaHi has to
+ // be an odd-numbered register, so the low bit will be set by the
+ // decode function below) indicates that we must decode as SQRSHR
+ // or UQRSHL, which both have a single Rda register field with all
+ // four bits.
+ unsigned Rda = fieldFromInstruction(Insn, 16, 4);
- Inst.addOperand(MCOperand::createImm(ARMCC::AL));
- Inst.addOperand(MCOperand::createReg(0));
- unsigned regs = fieldFromInstruction(Insn, 0, 8);
- if (regs == 0) {
- // Register list contains only VPR
- } else if (Inst.getOpcode() == ARM::VSCCLRMD) {
- unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) |
- (fieldFromInstruction(Insn, 22, 1) << 12);
- if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
- return MCDisassembler::Fail;
+ switch (Inst.getOpcode()) {
+ case ARM::MVE_ASRLr:
+ case ARM::MVE_SQRSHRL:
+ Inst.setOpcode(ARM::MVE_SQRSHR);
+ break;
+ case ARM::MVE_LSLLr:
+ case ARM::MVE_UQRSHLL:
+ Inst.setOpcode(ARM::MVE_UQRSHL);
+ break;
+ default:
+ llvm_unreachable("Unexpected starting opcode!");
}
- } else {
- unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) |
- fieldFromInstruction(Insn, 22, 1);
- // Registers past s31 are permitted and treated as being half of a d
- // register, though both halves of each d register must be present.
- unsigned max_reg = Vd + regs;
- if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))
- S = MCDisassembler::SoftFail;
- unsigned max_sreg = std::min(32u, max_reg);
- unsigned max_dreg = std::min(32u, max_reg / 2);
- for (unsigned i = Vd; i < max_sreg; ++i)
- if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder)))
- return MCDisassembler::Fail;
- for (unsigned i = 16; i < max_dreg; ++i)
- if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder)))
- return MCDisassembler::Fail;
- }
- Inst.addOperand(MCOperand::createReg(ARM::VPR));
- return S;
-}
+ // Rda as output parameter
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
+ return MCDisassembler::Fail;
-static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (RegNo > 7)
- return MCDisassembler::Fail;
+ // Rda again as input parameter
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
+ return MCDisassembler::Fail;
- unsigned Register = QPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::createReg(Register));
- return MCDisassembler::Success;
-}
+ // Rm, the amount to shift by
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
-static const MCPhysReg QQPRDecoderTable[] = {
- ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
- ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
-};
+ if (fieldFromInstruction(Insn, 6, 3) != 4)
+ return MCDisassembler::SoftFail;
-static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (RegNo > 6)
- return MCDisassembler::Fail;
+ if (Rda == Rm)
+ return MCDisassembler::SoftFail;
- unsigned Register = QQPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::createReg(Register));
- return MCDisassembler::Success;
-}
+ return S;
+ }
-static const MCPhysReg QQQQPRDecoderTable[] = {
- ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
- ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
-};
+ // Otherwise, we decode as whichever opcode our caller has already
+ // put into Inst. Those all look the same:
-static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (RegNo > 4)
+ // RdaLo,RdaHi as output parameters
+ if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
return MCDisassembler::Fail;
- unsigned Register = QQQQPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::createReg(Register));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
-
- // Parse VPT mask and encode it in the MCInst as an immediate with the same
- // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and
- // 't' as 0 and finish with a 1.
- unsigned Imm = 0;
- // We always start with a 't'.
- unsigned CurBit = 0;
- for (int i = 3; i >= 0; --i) {
- // If the bit we are looking at is not the same as last one, invert the
- // CurBit, if it is the same leave it as is.
- CurBit ^= (Val >> i) & 1U;
+ // RdaLo,RdaHi again as input parameters
+ if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
+ return MCDisassembler::Fail;
- // Encode the CurBit at the right place in the immediate.
- Imm |= (CurBit << i);
+ // Rm, the amount to shift by
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
- // If we are done, finish the encoding with a 1.
- if ((Val & ~(~0U << i)) == 0) {
- Imm |= 1U << i;
- break;
- }
+ if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
+ Inst.getOpcode() == ARM::MVE_UQRSHLL) {
+ unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
+ // Saturate, the bit position for saturation
+ Inst.addOperand(MCOperand::createImm(Saturate));
}
- Inst.addOperand(MCOperand::createImm(Imm));
-
return S;
}
-static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- // The vpred_r operand type includes an MQPR register field derived
- // from the encoding. But we don't actually want to add an operand
- // to the MCInst at this stage, because AddThumbPredicate will do it
- // later, and will infer the register number from the TIED_TO
- // constraint. So this is a deliberately empty decoder method that
- // will inhibit the auto-generated disassembly code from adding an
- // operand at all.
- return MCDisassembler::Success;
-}
+static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+ unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+ fieldFromInstruction(Insn, 13, 3));
+ unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
+ fieldFromInstruction(Insn, 1, 3));
+ unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
-[[maybe_unused]] static DecodeStatus
-DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address,
- const MCDisassembler *Decoder) {
- // Similar to above, we want to ensure that no operands are added for the
- // vpred operands. (This is marked "maybe_unused" for the moment; because
- // DecoderEmitter currently (wrongly) omits operands with no instruction bits,
- // the decoder doesn't actually call it yet. That will be addressed in a
- // future change.)
- return MCDisassembler::Success;
-}
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
+ return MCDisassembler::Fail;
-static DecodeStatus
-DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder) {
- Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
- return MCDisassembler::Success;
+ return S;
}
-static DecodeStatus
-DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
+template <bool scalar, OperandDecoder predicate_decoder>
+static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
- unsigned Code;
- switch (Val & 0x3) {
- case 0:
- Code = ARMCC::GE;
- break;
- case 1:
- Code = ARMCC::LT;
- break;
- case 2:
- Code = ARMCC::GT;
- break;
- case 3:
- Code = ARMCC::LE;
- break;
+ DecodeStatus S = MCDisassembler::Success;
+ Inst.addOperand(MCOperand::createReg(ARM::VPR));
+ unsigned Qn = fieldFromInstruction(Insn, 17, 3);
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ unsigned fc;
+
+ if (scalar) {
+ fc = fieldFromInstruction(Insn, 12, 1) << 2 |
+ fieldFromInstruction(Insn, 7, 1) |
+ fieldFromInstruction(Insn, 5, 1) << 1;
+ unsigned Rm = fieldFromInstruction(Insn, 0, 4);
+ if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else {
+ fc = fieldFromInstruction(Insn, 12, 1) << 2 |
+ fieldFromInstruction(Insn, 7, 1) |
+ fieldFromInstruction(Insn, 0, 1) << 1;
+ unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
+ fieldFromInstruction(Insn, 1, 3);
+ if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::createImm(Code));
- return MCDisassembler::Success;
-}
-static DecodeStatus
-DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder) {
- Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
- return MCDisassembler::Success;
+ if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createImm(ARMVCC::None));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(0));
+
+ return S;
}
-static DecodeStatus
-DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder) {
- unsigned Code;
- switch (Val) {
- default:
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+ Inst.addOperand(MCOperand::createReg(ARM::VPR));
+ unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- case 0:
- Code = ARMCC::EQ;
- break;
- case 1:
- Code = ARMCC::NE;
- break;
- case 4:
- Code = ARMCC::GE;
- break;
- case 5:
- Code = ARMCC::LT;
- break;
- case 6:
- Code = ARMCC::GT;
- break;
- case 7:
- Code = ARMCC::LE;
- break;
- }
-
- Inst.addOperand(MCOperand::createImm(Code));
- return MCDisassembler::Success;
+ return S;
}
-static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
+ Inst.addOperand(MCOperand::createReg(ARM::VPR));
+ Inst.addOperand(MCOperand::createReg(ARM::VPR));
+ return S;
+}
- unsigned DecodedVal = 64 - Val;
+static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
+ const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
+ fieldFromInstruction(Insn, 12, 3) << 8 |
+ fieldFromInstruction(Insn, 0, 8);
+ const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
+ unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
+ unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
+ unsigned S = fieldFromInstruction(Insn, 20, 1);
+ if (sign1 != sign2)
+ return MCDisassembler::Fail;
- switch (Inst.getOpcode()) {
- case ARM::MVE_VCVTf16s16_fix:
- case ARM::MVE_VCVTs16f16_fix:
- case ARM::MVE_VCVTf16u16_fix:
- case ARM::MVE_VCVTu16f16_fix:
- if (DecodedVal > 16)
+ // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
+ DecodeStatus DS = MCDisassembler::Success;
+ if ((!Check(DS,
+ DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
+ (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
+ return MCDisassembler::Fail;
+ if (TypeT3) {
+ Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
+ Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
+ } else {
+ Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
+ if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
return MCDisassembler::Fail;
- break;
- case ARM::MVE_VCVTf32s32_fix:
- case ARM::MVE_VCVTs32f32_fix:
- case ARM::MVE_VCVTf32u32_fix:
- case ARM::MVE_VCVTu32f32_fix:
- if (DecodedVal > 32)
+ if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
return MCDisassembler::Fail;
- break;
}
- Inst.addOperand(MCOperand::createImm(64 - Val));
+ return DS;
+}
+
+static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+ // Adding Rn, holding memory location to save/load to/from, the only argument
+ // that is being encoded.
+ // '$Rn' in the assembly.
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // An optional predicate, '$p' in the assembly.
+ DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder);
+ // An immediate that represents a floating point registers list. '$regs' in
+ // the assembly.
+ Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect.
return S;
}
-static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
- switch (Opcode) {
- case ARM::VSTR_P0_off:
- case ARM::VSTR_P0_pre:
- case ARM::VSTR_P0_post:
- case ARM::VLDR_P0_off:
- case ARM::VLDR_P0_pre:
- case ARM::VLDR_P0_post:
- return ARM::P0;
- case ARM::VSTR_FPSCR_NZCVQC_off:
- case ARM::VSTR_FPSCR_NZCVQC_pre:
- case ARM::VSTR_FPSCR_NZCVQC_post:
- case ARM::VLDR_FPSCR_NZCVQC_off:
- case ARM::VLDR_FPSCR_NZCVQC_pre:
- case ARM::VLDR_FPSCR_NZCVQC_post:
- return ARM::FPSCR;
- default:
- return 0;
- }
-}
+#include "ARMGenDisassemblerTables.inc"
-template <bool Writeback>
-static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- switch (Inst.getOpcode()) {
- case ARM::VSTR_FPSCR_pre:
- case ARM::VSTR_FPSCR_NZCVQC_pre:
- case ARM::VLDR_FPSCR_pre:
- case ARM::VLDR_FPSCR_NZCVQC_pre:
- case ARM::VSTR_FPSCR_off:
- case ARM::VSTR_FPSCR_NZCVQC_off:
- case ARM::VLDR_FPSCR_off:
- case ARM::VLDR_FPSCR_NZCVQC_off:
- case ARM::VSTR_FPSCR_post:
- case ARM::VSTR_FPSCR_NZCVQC_post:
- case ARM::VLDR_FPSCR_post:
- case ARM::VLDR_FPSCR_NZCVQC_post:
- const FeatureBitset &featureBits =
- Decoder->getSubtargetInfo().getFeatureBits();
+static MCDisassembler *createARMDisassembler(const Target &T,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) {
+ return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());
+}
- if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
+// Post-decoding checks
+static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
+ uint64_t Address, raw_ostream &CS,
+ uint32_t Insn,
+ DecodeStatus Result) {
+ switch (MI.getOpcode()) {
+ case ARM::HVC: {
+ // HVC is undefined if condition = 0xf otherwise upredictable
+ // if condition != 0xe
+ uint32_t Cond = (Insn >> 28) & 0xF;
+ if (Cond == 0xF)
return MCDisassembler::Fail;
+ if (Cond != 0xE)
+ return MCDisassembler::SoftFail;
+ return Result;
+ }
+ case ARM::t2ADDri:
+ case ARM::t2ADDri12:
+ case ARM::t2ADDrr:
+ case ARM::t2ADDrs:
+ case ARM::t2SUBri:
+ case ARM::t2SUBri12:
+ case ARM::t2SUBrr:
+ case ARM::t2SUBrs:
+ if (MI.getOperand(0).getReg() == ARM::SP &&
+ MI.getOperand(1).getReg() != ARM::SP)
+ return MCDisassembler::SoftFail;
+ return Result;
+ default:
+ return Result;
}
+}
- DecodeStatus S = MCDisassembler::Success;
- if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
- Inst.addOperand(MCOperand::createReg(Sysreg));
- unsigned Rn = fieldFromInstruction(Val, 16, 4);
- unsigned addr = fieldFromInstruction(Val, 0, 7) |
- (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
+ uint64_t Address) const {
+ // In Arm state, instructions are always 4 bytes wide, so there's no
+ // point in skipping any smaller number of bytes if an instruction
+ // can't be decoded.
+ if (!STI.hasFeature(ARM::ModeThumb))
+ return 4;
- if (Writeback) {
- if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- }
- if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
- return MCDisassembler::Fail;
+ // In a Thumb instruction stream, a halfword is a standalone 2-byte
+ // instruction if and only if its value is less than 0xE800.
+ // Otherwise, it's the first halfword of a 4-byte instruction.
+ //
+ // So, if we can see the upcoming halfword, we can judge on that
+ // basis, and maybe skip a whole 4-byte instruction that we don't
+ // know how to decode, without accidentally trying to interpret its
+ // second half as something else.
+ //
+ // If we don't have the instruction data available, we just have to
+ // recommend skipping the minimum sensible distance, which is 2
+ // bytes.
+ if (Bytes.size() < 2)
+ return 2;
- Inst.addOperand(MCOperand::createImm(ARMCC::AL));
- Inst.addOperand(MCOperand::createReg(0));
+ uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
+ Bytes.data(), InstructionEndianness);
+ return Insn16 < 0xE800 ? 2 : 4;
+}
- return S;
+DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
+ ArrayRef<uint8_t> Bytes,
+ uint64_t Address,
+ raw_ostream &CS) const {
+ if (STI.hasFeature(ARM::ModeThumb))
+ return getThumbInstruction(MI, Size, Bytes, Address, CS);
+ return getARMInstruction(MI, Size, Bytes, Address, CS);
}
-static inline DecodeStatus
-DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder, unsigned Rn,
- OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
- DecodeStatus S = MCDisassembler::Success;
+DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
+ ArrayRef<uint8_t> Bytes,
+ uint64_t Address,
+ raw_ostream &CS) const {
+ CommentStream = &CS;
- unsigned Qd = fieldFromInstruction(Val, 13, 3);
- unsigned addr = fieldFromInstruction(Val, 0, 7) |
- (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+ assert(!STI.hasFeature(ARM::ModeThumb) &&
+ "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
+ "mode!");
- if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
+ // We want to read exactly 4 bytes of data.
+ if (Bytes.size() < 4) {
+ Size = 0;
return MCDisassembler::Fail;
+ }
- return S;
-}
+ // Encoded as a 32-bit word in the stream.
+ uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),
+ InstructionEndianness);
-template <int shift>
-static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
- fieldFromInstruction(Val, 16, 3),
- DecodetGPRRegisterClass,
- DecodeTAddrModeImm7<shift>);
-}
+ // Calling the auto-generated decoder function.
+ DecodeStatus Result =
+ decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
+ }
-template <int shift>
-static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
- fieldFromInstruction(Val, 16, 4),
- DecoderGPRRegisterClass,
- DecodeT2AddrModeImm7<shift,1>);
-}
+ struct DecodeTable {
+ const uint8_t *P;
+ bool DecodePred;
+ };
-template <int shift>
-static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
- fieldFromInstruction(Val, 17, 3),
- DecodeMQPRRegisterClass,
- DecodeMveAddrModeQ<shift>);
+ const DecodeTable Tables[] = {
+ {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
+ {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
+ {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
+ {DecoderTablev8Crypto32, false},
+ };
+
+ for (auto Table : Tables) {
+ Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ // Add a fake predicate operand, because we share these instruction
+ // definitions with Thumb2 where these instructions are predicable.
+ if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
+ return MCDisassembler::Fail;
+ return Result;
+ }
+ }
+
+ Result =
+ decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
+ }
+
+ Size = 4;
+ return MCDisassembler::Fail;
}
-template <unsigned MinLog, unsigned MaxLog>
-static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
+// Thumb1 instructions don't have explicit S bits. Rather, they
+// implicitly set CPSR. Since it's not represented in the encoding, the
+// auto-generated decoder won't inject the CPSR operand. We need to fix
+// that as a post-pass.
+void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
+ const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
+ MCInst::iterator I = MI.begin();
+ for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) {
+ if (I == MI.end())
+ break;
+ if (MCID.operands()[i].isOptionalDef() &&
+ MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
+ if (i > 0 && MCID.operands()[i - 1].isPredicate())
+ continue;
+ MI.insert(I,
+ MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
+ return;
+ }
+ }
- if (Val < MinLog || Val > MaxLog)
- return MCDisassembler::Fail;
+ MI.insert(I, MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR));
+}
- Inst.addOperand(MCOperand::createImm(1LL << Val));
- return S;
+bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
+ const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
+ for (unsigned i = 0; i < MCID.NumOperands; ++i) {
+ if (ARM::isVpred(MCID.operands()[i].OperandType))
+ return true;
+ }
+ return false;
}
-template <unsigned start>
-static DecodeStatus
-DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
+// Most Thumb instructions don't have explicit predicates in the
+// encoding, but rather get their predicates from IT context. We need
+// to fix up the predicate operands using this context information as a
+// post-pass.
+MCDisassembler::DecodeStatus
+ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
+ MCDisassembler::DecodeStatus S = Success;
- Inst.addOperand(MCOperand::createImm(start + Val));
+ const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
- return S;
-}
+ // A few instructions actually have predicates encoded in them. Don't
+ // try to overwrite it if we're seeing one of those.
+ switch (MI.getOpcode()) {
+ case ARM::tBcc:
+ case ARM::t2Bcc:
+ case ARM::tCBZ:
+ case ARM::tCBNZ:
+ case ARM::tCPS:
+ case ARM::t2CPS3p:
+ case ARM::t2CPS2p:
+ case ARM::t2CPS1p:
+ case ARM::t2CSEL:
+ case ARM::t2CSINC:
+ case ARM::t2CSINV:
+ case ARM::t2CSNEG:
+ case ARM::tMOVSr:
+ case ARM::tSETEND:
+ // Some instructions (mostly conditional branches) are not
+ // allowed in IT blocks.
+ if (ITBlock.instrInITBlock())
+ S = SoftFail;
+ else
+ return Success;
+ break;
+ case ARM::t2HINT:
+ if (MI.getOperand(0).getImm() == 0x10 &&
+ (FeatureBits[ARM::FeatureRAS]) != 0)
+ S = SoftFail;
+ break;
+ case ARM::tB:
+ case ARM::t2B:
+ case ARM::t2TBB:
+ case ARM::t2TBH:
+ // Some instructions (mostly unconditional branches) can
+ // only appears at the end of, or outside of, an IT.
+ if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
+ S = SoftFail;
+ break;
+ default:
+ break;
+ }
-static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
- unsigned Rt = fieldFromInstruction(Insn, 0, 4);
- unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
- unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
- fieldFromInstruction(Insn, 13, 3));
- unsigned index = fieldFromInstruction(Insn, 4, 1);
+ // Warn on non-VPT predicable instruction in a VPT block and a VPT
+ // predicable instruction in an IT block
+ if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||
+ (isVectorPredicable(MI) && ITBlock.instrInITBlock()))
+ S = SoftFail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
- return MCDisassembler::Fail;
+ // If we're in an IT/VPT block, base the predicate on that. Otherwise,
+ // assume a predicate of AL.
+ unsigned CC = ARMCC::AL;
+ unsigned VCC = ARMVCC::None;
+ if (ITBlock.instrInITBlock()) {
+ CC = ITBlock.getITCC();
+ ITBlock.advanceITState();
+ } else if (VPTBlock.instrInVPTBlock()) {
+ VCC = VPTBlock.getVPTPred();
+ VPTBlock.advanceVPTState();
+ }
- return S;
-}
+ const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
-static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
- unsigned Rt = fieldFromInstruction(Insn, 0, 4);
- unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
- unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
- fieldFromInstruction(Insn, 13, 3));
- unsigned index = fieldFromInstruction(Insn, 4, 1);
+ MCInst::iterator CCI = MI.begin();
+ for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) {
+ if (MCID.operands()[i].isPredicate() || CCI == MI.end())
+ break;
+ }
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
- return MCDisassembler::Fail;
+ if (MCID.isPredicable()) {
+ CCI = MI.insert(CCI, MCOperand::createImm(CC));
+ ++CCI;
+ if (CC == ARMCC::AL)
+ MI.insert(CCI, MCOperand::createReg(ARM::NoRegister));
+ else
+ MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
+ } else if (CC != ARMCC::AL) {
+ Check(S, SoftFail);
+ }
+
+ MCInst::iterator VCCI = MI.begin();
+ unsigned VCCPos;
+ for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) {
+ if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end())
+ break;
+ }
+
+ if (isVectorPredicable(MI)) {
+ VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
+ ++VCCI;
+ if (VCC == ARMVCC::None)
+ VCCI = MI.insert(VCCI, MCOperand::createReg(0));
+ else
+ VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
+ ++VCCI;
+ VCCI = MI.insert(VCCI, MCOperand::createReg(0));
+ ++VCCI;
+ if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
+ int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO);
+ assert(TiedOp >= 0 &&
+ "Inactive register in vpred_r is not tied to an output!");
+ // Copy the operand to ensure it's not invalidated when MI grows.
+ MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
+ }
+ } else if (VCC != ARMVCC::None) {
+ Check(S, SoftFail);
+ }
return S;
}
-static DecodeStatus
-DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
+// Thumb VFP instructions are a special case. Because we share their
+// encodings between ARM and Thumb modes, and they are predicable in ARM
+// mode, the auto-generated decoder will give them an (incorrect)
+// predicate operand. We need to rewrite these operands based on the IT
+// context as a post-pass.
+void ARMDisassembler::UpdateThumbVFPPredicate(DecodeStatus &S,
+ MCInst &MI) const {
+ unsigned CC;
+ CC = ITBlock.getITCC();
+ if (CC == 0xF)
+ CC = ARMCC::AL;
+ if (ITBlock.instrInITBlock())
+ ITBlock.advanceITState();
+ else if (VPTBlock.instrInVPTBlock()) {
+ CC = VPTBlock.getVPTPred();
+ VPTBlock.advanceVPTState();
+ }
- unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
- unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
- unsigned Rm = fieldFromInstruction(Insn, 12, 4);
+ const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
+ ArrayRef<MCOperandInfo> OpInfo = MCID.operands();
+ MCInst::iterator I = MI.begin();
+ unsigned short NumOps = MCID.NumOperands;
+ for (unsigned i = 0; i < NumOps; ++i, ++I) {
+ if (OpInfo[i].isPredicate()) {
+ if (CC != ARMCC::AL && !MCID.isPredicable())
+ Check(S, SoftFail);
+ I->setImm(CC);
+ ++I;
+ if (CC == ARMCC::AL)
+ I->setReg(ARM::NoRegister);
+ else
+ I->setReg(ARM::CPSR);
+ return;
+ }
+ }
+}
- if (RdaHi == 14) {
- // This value of RdaHi (really indicating pc, because RdaHi has to
- // be an odd-numbered register, so the low bit will be set by the
- // decode function below) indicates that we must decode as SQRSHR
- // or UQRSHL, which both have a single Rda register field with all
- // four bits.
- unsigned Rda = fieldFromInstruction(Insn, 16, 4);
+DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
+ ArrayRef<uint8_t> Bytes,
+ uint64_t Address,
+ raw_ostream &CS) const {
+ CommentStream = &CS;
- switch (Inst.getOpcode()) {
- case ARM::MVE_ASRLr:
- case ARM::MVE_SQRSHRL:
- Inst.setOpcode(ARM::MVE_SQRSHR);
- break;
- case ARM::MVE_LSLLr:
- case ARM::MVE_UQRSHLL:
- Inst.setOpcode(ARM::MVE_UQRSHL);
- break;
- default:
- llvm_unreachable("Unexpected starting opcode!");
- }
+ assert(STI.hasFeature(ARM::ModeThumb) &&
+ "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
- // Rda as output parameter
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
- return MCDisassembler::Fail;
+ // We want to read exactly 2 bytes of data.
+ if (Bytes.size() < 2) {
+ Size = 0;
+ return MCDisassembler::Fail;
+ }
- // Rda again as input parameter
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
- return MCDisassembler::Fail;
+ uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
+ Bytes.data(), InstructionEndianness);
+ DecodeStatus Result =
+ decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 2;
+ Check(Result, AddThumbPredicate(MI));
+ return Result;
+ }
- // Rm, the amount to shift by
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
- return MCDisassembler::Fail;
+ Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
+ STI);
+ if (Result) {
+ Size = 2;
+ bool InITBlock = ITBlock.instrInITBlock();
+ Check(Result, AddThumbPredicate(MI));
+ AddThumb1SBit(MI, InITBlock);
+ return Result;
+ }
- if (fieldFromInstruction (Insn, 6, 3) != 4)
- return MCDisassembler::SoftFail;
+ Result =
+ decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 2;
- if (Rda == Rm)
- return MCDisassembler::SoftFail;
+ // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
+ // the Thumb predicate.
+ if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
+ Result = MCDisassembler::SoftFail;
- return S;
- }
+ Check(Result, AddThumbPredicate(MI));
- // Otherwise, we decode as whichever opcode our caller has already
- // put into Inst. Those all look the same:
+ // If we find an IT instruction, we need to parse its condition
+ // code and mask operands so that we can apply them correctly
+ // to the subsequent instructions.
+ if (MI.getOpcode() == ARM::t2IT) {
+ unsigned Firstcond = MI.getOperand(0).getImm();
+ unsigned Mask = MI.getOperand(1).getImm();
+ ITBlock.setITState(Firstcond, Mask);
- // RdaLo,RdaHi as output parameters
- if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
- return MCDisassembler::Fail;
+ // An IT instruction that would give a 'NV' predicate is unpredictable.
+ if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
+ CS << "unpredictable IT predicate sequence";
+ }
- // RdaLo,RdaHi again as input parameters
- if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
- return MCDisassembler::Fail;
+ return Result;
+ }
- // Rm, the amount to shift by
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ // We want to read exactly 4 bytes of data.
+ if (Bytes.size() < 4) {
+ Size = 0;
return MCDisassembler::Fail;
-
- if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
- Inst.getOpcode() == ARM::MVE_UQRSHLL) {
- unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
- // Saturate, the bit position for saturation
- Inst.addOperand(MCOperand::createImm(Saturate));
}
- return S;
-}
+ uint32_t Insn32 =
+ (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
+ Bytes.data() + 2, InstructionEndianness);
-static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
- unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
- fieldFromInstruction(Insn, 13, 3));
- unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
- fieldFromInstruction(Insn, 1, 3));
- unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
+ Result = decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
- return MCDisassembler::Fail;
- if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
- return MCDisassembler::Fail;
+ // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
+ // the VPT predicate.
+ if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
+ Result = MCDisassembler::SoftFail;
- return S;
-}
+ Check(Result, AddThumbPredicate(MI));
-template <bool scalar, OperandDecoder predicate_decoder>
-static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
- Inst.addOperand(MCOperand::createReg(ARM::VPR));
- unsigned Qn = fieldFromInstruction(Insn, 17, 3);
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
- return MCDisassembler::Fail;
+ if (isVPTOpcode(MI.getOpcode())) {
+ unsigned Mask = MI.getOperand(0).getImm();
+ VPTBlock.setVPTState(Mask);
+ }
- unsigned fc;
+ return Result;
+ }
- if (scalar) {
- fc = fieldFromInstruction(Insn, 12, 1) << 2 |
- fieldFromInstruction(Insn, 7, 1) |
- fieldFromInstruction(Insn, 5, 1) << 1;
- unsigned Rm = fieldFromInstruction(Insn, 0, 4);
- if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
- return MCDisassembler::Fail;
- } else {
- fc = fieldFromInstruction(Insn, 12, 1) << 2 |
- fieldFromInstruction(Insn, 7, 1) |
- fieldFromInstruction(Insn, 0, 1) << 1;
- unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
- fieldFromInstruction(Insn, 1, 3);
- if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
- return MCDisassembler::Fail;
+ Result =
+ decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ bool InITBlock = ITBlock.instrInITBlock();
+ Check(Result, AddThumbPredicate(MI));
+ AddThumb1SBit(MI, InITBlock);
+ return Result;
}
- if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
- return MCDisassembler::Fail;
+ Result =
+ decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ Check(Result, AddThumbPredicate(MI));
+ return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
+ }
- Inst.addOperand(MCOperand::createImm(ARMVCC::None));
- Inst.addOperand(MCOperand::createReg(0));
- Inst.addOperand(MCOperand::createImm(0));
+ if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
+ Result =
+ decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ UpdateThumbVFPPredicate(Result, MI);
+ return Result;
+ }
+ }
- return S;
-}
+ Result =
+ decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
-static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
- Inst.addOperand(MCOperand::createReg(ARM::VPR));
- unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- return S;
-}
+ if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
+ Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
+ STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ Check(Result, AddThumbPredicate(MI));
+ return Result;
+ }
+ }
-static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
- Inst.addOperand(MCOperand::createReg(ARM::VPR));
- Inst.addOperand(MCOperand::createReg(ARM::VPR));
- return S;
-}
+ if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
+ uint32_t NEONLdStInsn = Insn32;
+ NEONLdStInsn &= 0xF0FFFFFF;
+ NEONLdStInsn |= 0x04000000;
+ Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
+ Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ Check(Result, AddThumbPredicate(MI));
+ return Result;
+ }
+ }
-static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
- const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
- fieldFromInstruction(Insn, 12, 3) << 8 |
- fieldFromInstruction(Insn, 0, 8);
- const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
- unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
- unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
- unsigned S = fieldFromInstruction(Insn, 20, 1);
- if (sign1 != sign2)
- return MCDisassembler::Fail;
+ if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
+ uint32_t NEONDataInsn = Insn32;
+ NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
+ NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
+ NEONDataInsn |= 0x12000000; // Set bits 28 and 25
+ Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
+ Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ Check(Result, AddThumbPredicate(MI));
+ return Result;
+ }
- // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
- DecodeStatus DS = MCDisassembler::Success;
- if ((!Check(DS,
- DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
- (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
- return MCDisassembler::Fail;
- if (TypeT3) {
- Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
- Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
- } else {
- Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
- if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
- return MCDisassembler::Fail;
- if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
- return MCDisassembler::Fail;
- }
+ uint32_t NEONCryptoInsn = Insn32;
+ NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
+ NEONCryptoInsn |=
+ (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
+ NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
+ Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
+ Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
- return DS;
-}
+ uint32_t NEONv8Insn = Insn32;
+ NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
+ Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
+ this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+ }
-static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- DecodeStatus S = MCDisassembler::Success;
+ uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
+ const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
+ ? DecoderTableThumb2CDE32
+ : DecoderTableThumb2CoProc32;
+ Result = decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ Check(Result, AddThumbPredicate(MI));
+ return Result;
+ }
- const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- // Adding Rn, holding memory location to save/load to/from, the only argument
- // that is being encoded.
- // '$Rn' in the assembly.
- if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
- return MCDisassembler::Fail;
- // An optional predicate, '$p' in the assembly.
- DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder);
- // An immediate that represents a floating point registers list. '$regs' in
- // the assembly.
- Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect.
+ // Advance IT state to prevent next instruction inheriting
+ // the wrong IT state.
+ if (ITBlock.instrInITBlock())
+ ITBlock.advanceITState();
+ Size = 0;
+ return MCDisassembler::Fail;
+}
- return S;
+extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
+LLVMInitializeARMDisassembler() {
+ TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
+ createARMDisassembler);
+ TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
+ createARMDisassembler);
+ TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
+ createARMDisassembler);
+ TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
+ createARMDisassembler);
}
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