[llvm] [AArch64] Allow peephole to optimize AND + signed compare with 0 (PR #153608)

[via llvm-commits]

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@@ -1921,7 +1998,8 @@ static bool canInstrSubstituteCmpInstr(MachineInstr &MI, MachineInstr &CmpInstr,
   // 1) MI and CmpInstr set N and V to the same value.
   // 2) If MI is add/sub with no-signed-wrap, it produces a poison value when
   //    signed overflow occurs, so CmpInstr could still be simplified away.
-  if (NZVCUsed->V && !MI.getFlag(MachineInstr::NoSWrap))
+  // 3) ANDS/BICS on AArch64 always sets V to 0, so it is safe to look through.
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AZero13 wrote:

AND instructions are not tagged as no overflow

And, the peephole as is checks for no touching of V and C.

However, and instructions on AArch64 (NOT ARM as in the 32 bit ISA) ALWAYS set C and V to 0.

As to when the C being 0 can be useful, I'm trying to figure that out and that's for another PR, but for now,know that cmp with 0 also always clears V, but the peephole doesn't know that.

https://github.com/llvm/llvm-project/pull/153608