[llvm] [AMDGPU] Fix hw stage metadata setting for unsigned values (PR #154502)
Ana Mihajlovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 22 07:34:37 PDT 2025
https://github.com/mihajlovicana updated https://github.com/llvm/llvm-project/pull/154502
>From a242301f0ebb18e98607c368ab7a49b2fba1d51a Mon Sep 17 00:00:00 2001
From: "Mihajlovic, Ana" <Ana.Mihajlovic at amd.com>
Date: Tue, 12 Aug 2025 09:54:47 +0200
Subject: [PATCH 1/4] [AMDGPU] Fix hw stage metadata setting for unsigned
values (#3323)
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 7 +++---
.../Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp | 11 +++++++++
.../Target/AMDGPU/Utils/AMDGPUPALMetadata.h | 1 +
.../CodeGen/AMDGPU/lds-size-pal-metadata.ll | 24 +++++++++++++++++++
4 files changed, 40 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 36c0d1cbcea22..3e799e3ae7ecc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1440,9 +1440,10 @@ static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD,
MD->setComputeRegisters(".dynamic_vgpr_en", true);
}
- MD->setHwStage(CC, ".lds_size",
- (unsigned)(CurrentProgramInfo.LdsSize *
- getLdsDwGranularity(ST) * sizeof(uint32_t)));
+ MD->updateHwStageMaximum(
+ CC, ".lds_size",
+ (unsigned)(CurrentProgramInfo.LdsSize * getLdsDwGranularity(ST) *
+ sizeof(uint32_t)));
}
// This is the equivalent of EmitProgramInfoSI above, but for when the OS type
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
index fd6253daa327a..8d1b0e6dac2d6 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
@@ -1061,6 +1061,17 @@ VersionTuple AMDGPUPALMetadata::getPALVersion() {
return VersionTuple(getPALVersion(0), getPALVersion(1));
}
+// Set the field in a given .hardware_stages entry to a maximum value
+void AMDGPUPALMetadata::updateHwStageMaximum(unsigned CC, StringRef field,
+ unsigned Val) {
+ auto HwStageFieldMapNode = getHwStage(CC);
+ auto It = HwStageFieldMapNode.find(field);
+ if (It == HwStageFieldMapNode.end())
+ HwStageFieldMapNode[field] = Val;
+ else
+ It->second = std::max<unsigned>(It->second.getUInt(), Val);
+}
+
// Set the field in a given .hardware_stages entry
void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) {
getHwStage(CC)[field] = Val;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h
index 4830db5fda50b..e50150cc8de94 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h
@@ -156,6 +156,7 @@ class AMDGPUPALMetadata {
unsigned getPALMinorVersion();
VersionTuple getPALVersion();
+ void updateHwStageMaximum(unsigned CC, StringRef field, unsigned Val);
void setHwStage(unsigned CC, StringRef field, unsigned Val);
void setHwStage(unsigned CC, StringRef field, bool Val);
void setHwStage(unsigned CC, StringRef field, msgpack::Type Type,
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
new file mode 100644
index 0000000000000..75fd5fc45ab3e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1300 < %s | FileCheck -check-prefix=PAL %s
+
+ at x = addrspace(3) global i32 undef
+
+; PAL: .hardware_stages:
+; PAL: .lds_size: 0x400
+; PAL: .shader_functions:
+; PAL: f1:
+; PAL: .lds_size: 0x4
+; PAL: f2:
+; PAL: .lds_size: 0
+
+define amdgpu_gfx void @f1(i32 %val) {
+ store i32 %val, ptr addrspace(3) @x
+ ret void
+}
+
+define amdgpu_gfx void @f2(i32 %a, ptr addrspace(1) %ptr) {
+ store i32 %a, ptr addrspace(1) %ptr
+ ret void
+}
+
+!amdgpu.pal.metadata.msgpack = !{!8}
+!8 = !{!"\82\B0amdpal.pipelines\91\8A\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C3\AA.tgid_y_en\C3\AA.tgid_z_en\C3\AF.tidig_comp_cnt\00\B0.hardware_stages\81\A3.cs\8D\AF.checksum_value\00\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93 \01\01\AD.trap_present\00\B2.user_data_reg_map\DC\00 \CE\10\00\00\00\CE\10\00\00\06\CE\FF\FF\FF\FF\00\01\02\03\04\05\06\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\10\00\00\02\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\AB.user_sgprs\10\AB.vgpr_limit\CC\80\AF.wavefront_size \AF.wg_round_robin\C2\B7.internal_pipeline_hash\92\CF\F6\B5\A6D\E3\BE\9D\D6\CFF\\=l\09\AB\F0#\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\00\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CD\FF\FF\A5.type\A2Cs\B0.user_data_limit\07\A9.uses_cps\C3\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF-ua\DD\EA7\19\94\CF\80\16\9A\FC\9B\A6\1Dk\AD.llpc_version\A477.4\AEamdpal.version\92\03\00"}
\ No newline at end of file
>From 6bcd77e4ff6a82fb889ed5ed2d5cca26231361f3 Mon Sep 17 00:00:00 2001
From: Ana Mihajlovic <Ana.Mihajlovic at amd.com>
Date: Wed, 20 Aug 2025 11:42:05 +0200
Subject: [PATCH 2/4] update test
---
llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
index 75fd5fc45ab3e..ff260997f3357 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
@@ -1,9 +1,10 @@
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1300 < %s | FileCheck -check-prefix=PAL %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=PAL %s
@x = addrspace(3) global i32 undef
; PAL: .hardware_stages:
-; PAL: .lds_size: 0x400
+; PAL: .lds_size: 0x200
; PAL: .shader_functions:
; PAL: f1:
; PAL: .lds_size: 0x4
@@ -21,4 +22,4 @@ define amdgpu_gfx void @f2(i32 %a, ptr addrspace(1) %ptr) {
}
!amdgpu.pal.metadata.msgpack = !{!8}
-!8 = !{!"\82\B0amdpal.pipelines\91\8A\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C3\AA.tgid_y_en\C3\AA.tgid_z_en\C3\AF.tidig_comp_cnt\00\B0.hardware_stages\81\A3.cs\8D\AF.checksum_value\00\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93 \01\01\AD.trap_present\00\B2.user_data_reg_map\DC\00 \CE\10\00\00\00\CE\10\00\00\06\CE\FF\FF\FF\FF\00\01\02\03\04\05\06\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\10\00\00\02\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\AB.user_sgprs\10\AB.vgpr_limit\CC\80\AF.wavefront_size \AF.wg_round_robin\C2\B7.internal_pipeline_hash\92\CF\F6\B5\A6D\E3\BE\9D\D6\CFF\\=l\09\AB\F0#\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\00\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CD\FF\FF\A5.type\A2Cs\B0.user_data_limit\07\A9.uses_cps\C3\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF-ua\DD\EA7\19\94\CF\80\16\9A\FC\9B\A6\1Dk\AD.llpc_version\A477.4\AEamdpal.version\92\03\00"}
\ No newline at end of file
+!8 = !{!"\82\B0amdpal.pipelines\91\8A\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C3\AA.tgid_y_en\C3\AA.tgid_z_en\C3\AF.tidig_comp_cnt\00\B0.hardware_stages\81\A3.cs\8D\AF.checksum_value\00\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93 \01\01\AD.trap_present\00\B2.user_data_reg_map\DC\00 \CE\10\00\00\00\CE\10\00\00\06\CE\FF\FF\FF\FF\00\01\02\03\04\05\06\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\10\00\00\02\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\AB.user_sgprs\10\AB.vgpr_limit\CC\80\AF.wavefront_size \AF.wg_round_robin\C2\B7.internal_pipeline_hash\92\CF\F6\B5\A6D\E3\BE\9D\D6\CFF\\=l\09\AB\F0#\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\00\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CD\FF\FF\A5.type\A2Cs\B0.user_data_limit\07\A9.uses_cps\C3\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF-ua\DD\EA7\19\94\CF\80\16\9A\FC\9B\A6\1Dk\AD.llpc_version\A477.4\AEamdpal.version\92\03\00"}
>From 4a0605c5b4d3a8345adbcfb64dbad62cfb8eccd8 Mon Sep 17 00:00:00 2001
From: Ana Mihajlovic <Ana.Mihajlovic at amd.com>
Date: Wed, 20 Aug 2025 12:39:37 +0200
Subject: [PATCH 3/4] update
---
llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
index 8d1b0e6dac2d6..fea4c116e765f 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
@@ -1064,7 +1064,7 @@ VersionTuple AMDGPUPALMetadata::getPALVersion() {
// Set the field in a given .hardware_stages entry to a maximum value
void AMDGPUPALMetadata::updateHwStageMaximum(unsigned CC, StringRef field,
unsigned Val) {
- auto HwStageFieldMapNode = getHwStage(CC);
+ msgpack::MapDocNode HwStageFieldMapNode = getHwStage(CC);
auto It = HwStageFieldMapNode.find(field);
if (It == HwStageFieldMapNode.end())
HwStageFieldMapNode[field] = Val;
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
index ff260997f3357..9bcf887a3034c 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=PAL %s
- at x = addrspace(3) global i32 undef
+ at x = addrspace(3) global i32 poison
; PAL: .hardware_stages:
; PAL: .lds_size: 0x200
>From 4b15bbfeaee5960ca0602371636f809f7249d9f0 Mon Sep 17 00:00:00 2001
From: Ana Mihajlovic <Ana.Mihajlovic at amd.com>
Date: Fri, 22 Aug 2025 16:34:10 +0200
Subject: [PATCH 4/4] add comment to test
---
llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
index 9bcf887a3034c..270c17fc24c7e 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=PAL %s
+;test if zero lds_size of f2 doesn't overwrite f1
@x = addrspace(3) global i32 poison
; PAL: .hardware_stages:
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