[llvm] [WIP][SPARC] Weaken emitted barriers for atomic ops (PR #154950)

[via llvm-commits]

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@@ -1957,12 +1957,31 @@ def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
 
-// store bar for all atomic_fence in V8.
-let Predicates = [HasNoV9] in
+// All load-type operations in V8 comes with implicit acquire semantics.
+let Predicates = [HasNoV9] in {
+  // Acquire -> nop
+  def : Pat<(atomic_fence (i32 4), timm), (NOP)>;
+  // Release / AcqRel -> stbar
+  def : Pat<(atomic_fence (i32 5), timm), (STBAR)>;
+  // AcqRel and stronger -> stbar; ldstub [%sp-1], %g0
+  // FIXME how to actually emit the ldstub?
   def : Pat<(atomic_fence timm, timm), (STBAR)>;
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koachan wrote:

Currently LLVM emits buggy SC barriers on V8; it should be a two instruction sequence but it only emits the `stbar` without the following `ldstub`, and I haven't figured out to convince it to emit the `ldstub` too.
Any advice of what should I do here?

https://github.com/llvm/llvm-project/pull/154950