[llvm] [DAG] Constant fold ISD::FSHL/FSHR nodes (PR #154480)

[Simon Pilgrim via llvm-commits]

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@@ -11281,6 +11281,11 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) {
   unsigned BitWidth = VT.getScalarSizeInBits();
   SDLoc DL(N);
 
+  // fold (fshl C0, C1, C2) -> C3
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RKSimon wrote:

fshl/fshr

https://github.com/llvm/llvm-project/pull/154480