[llvm] [DAG] fix wrong type check in DAGCombiner::visitSRA (PR #153762)

[via llvm-commits]

woruyu wrote:

Thank you for the DAG! @akiva-pripas, however, I tried to create a lit test that hits this change, but it’s very hard to reproduce reliably. Would it be acceptable to land the fix without a test?(just for trade-off)
the smallest testcase, but most of backend TLI.isTruncateFree return false for vec-type, hard to do this, High cost
```llvm
; RUN: llc -mtriple=x86_64-pc-linux-gnu -mattr=+avx512f -O2 < %s | FileCheck %s

define void @extract_bit31_mask_v8i64(<8 x i64>* %dst, <8 x i64>* %src) {


entry:
  %x = load <8 x i64>, <8 x i64>* %src, align 64
  %v31 = shufflevector <8 x i64> <i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31>,
                        <8 x i64> undef,
                        <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %v63 = shufflevector <8 x i64> <i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63>,
                        <8 x i64> undef,
                        <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>

  %shr = lshr <8 x i64> %x, %v31
%shl = shl <8 x i64> %shr,
            <i64 62, i64 62, i64 62, i64 62,
             i64 62, i64 62, i64 62, i64 62>

  %sra = ashr <8 x i64> %shl, %v63
  store <8 x i64> %sra, <8 x i64>* %dst, align 64
  ret void
}

``` 

https://github.com/llvm/llvm-project/pull/153762