[llvm] [RISCV] Loosen the requirement of shadow stack codegen to Zimop (PR #152251)

[Ming-Yi Lai via llvm-commits]

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@@ -62,6 +62,26 @@ defm SSAMOSWAP_W  : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
 let Predicates = [HasStdExtZicfiss, IsRV64] in
 defm SSAMOSWAP_D  : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
 
+let Predicates = [HasStdExtZimop] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in
+def PseudoMOP_SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
+                     "mop.rr.7", "$rs2"> {
+  let rd = 0b00000;
+  let rs1 = 0b00000;
+}
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1 in
+def PseudoMOP_SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "mop.r.28",
+                       "$rs1"> {
+  let rd = 0;
+  let imm12 = 0b110011011100;
+}
+}
+
+let Predicates = [HasStdExtZcmop] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in
+def PseudoMOP_C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.mop.1">;
+}
+
----------------
mylai-mtk wrote:

Hi, thanks for the effort to fill-in all these bits of information, but this is not what I'm expecting. What I was expecting are pure compiler pseudos that are only usable in the compiler pipeline, but not in the assembler/disassembler/... . What you created here are "real" (not pseudo) insns that expands to MOP insns. 

What I was expecting to see was something like:
```
def PseudoMOP_SSPUSH : Pseudo<(outs), (ins GPRX1X5:$ra), []>,
    PseudoInstExpansion<(MOPRR7 GPRX0, GPRX0, GPRX1X5:$ra)>;
```
This creates a compiler-only pseudo insn that is only usable in the compiler pipeline, and can be auto-expanded to the correct MOP insn during emission.

By using this methodology, I hope the following could be achieved:

+ Avoid directly emitting Zicfiss insns for the sake of limiting Zicfiss insns to just Zicfiss infras -> Use pseudo insns instead of Zicfiss insns [v].
+ Provide a method that allows easy identifying of these insns as Zicfiss insns in the compiler pipeline to facilitate possible future manipulations -> The pseudo insns have their allocated in-compiler insn numbers that are different from those of plain MOP insns so it's easy to identify them in the compiler, e.g `RISCV::PseudoMOP_SSPUSH` vs `RISCV::MOPRR7` [v].
+ The implementation should be easy to maintain -> The tablegen `Pseudo<>, PseudoInstExpansion<>` implementation is a one-liner and contains only the necessary information to allow insn instantiation and emission. Most importantly, no bit pattern nor textual format is in it, so we don't need to maintain these information. [v]

So I guess if the tablegen methodology compiles, everything would be fine and the goals be satisfied.

About assemblers/disassemblers, I think supporting these scenarios should be enabled by the real Zicfiss/MOP extension implementations, since users of these tools should have a clear understanding of the ISA he/she is targeting so he/she can deal with those programs written in machine-level insns. This means he/she needs to set the correct ISA extensions when working with these tools, and here (in this PR and thus just the compiler pipeline) all we need to do is just not to break the framework so normal Zicfiss/MOP extension implementations would enable the assemblers and disassemblers to function properly if the ISA extension is enabled.

https://github.com/llvm/llvm-project/pull/152251