[llvm] [AMDGPU] Add test to show failure with SRC_*_HI registers. NFC. (PR #154828)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

I.e., the definition should look like:
```
 multiclass ApertureRegister<string name, bits<8> regIdx> {
   let isConstant = true in {
     // FIXME: We shouldn't need to define subregisters for these (nor add them to any 16 bit
     //  register classes), but if we don't it seems to confuse the TableGen
     //  backend and we end up with a lot of weird register pressure sets and classes.
     defm _LO : SIRegLoHi16 <name, regIdx>;
+    let isArtificial = 1 in
     defm _HI : SIRegLoHi16 <"", regIdx>;

     def "" : RegisterWithSubRegs<name, [!cast<Register>(NAME#_LO), !cast<Register>(NAME#_HI)]> {
       let Namespace = "AMDGPU";
       let SubRegIndices = [sub0, sub1];
       let HWEncoding = !cast<Register>(NAME#_LO).HWEncoding;
+      let CoveredBySubRegs = 0;
     }
   } // isConstant = true
 }
```
But that creates unwanted `AMDGPU::RegisterPressureSets::SReg_32_XM0_with_hi16` even though `SReg_32_XM0` is guarded with `GeneratePressureSet = 0`. That is where tablegen backend needs some fixes I guess.

https://github.com/llvm/llvm-project/pull/154828