[llvm] [RISCV] Use llvm_anyint_ty instead of llvm_any_type for scalar intrinsics. NFC (PR #154816)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/154816

None

>From de4a739cc4c91fca4e8624eb49e358f36979e8ae Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 21 Aug 2025 10:50:24 -0700
Subject: [PATCH 1/2] [RISCV] Add riscv_masked_atomicrmw_*_i64 to
 getTgtMemIntrinsic.

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4a1db80076530..ff625a8bcda30 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1809,6 +1809,15 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::riscv_masked_atomicrmw_umax_i32:
   case Intrinsic::riscv_masked_atomicrmw_umin_i32:
   case Intrinsic::riscv_masked_cmpxchg_i32:
+  case Intrinsic::riscv_masked_atomicrmw_xchg_i64:
+  case Intrinsic::riscv_masked_atomicrmw_add_i64:
+  case Intrinsic::riscv_masked_atomicrmw_sub_i64:
+  case Intrinsic::riscv_masked_atomicrmw_nand_i64:
+  case Intrinsic::riscv_masked_atomicrmw_max_i64:
+  case Intrinsic::riscv_masked_atomicrmw_min_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umax_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umin_i64:
+  case Intrinsic::riscv_masked_cmpxchg_i64:
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     Info.memVT = MVT::i32;
     Info.ptrVal = I.getArgOperand(0);

>From 4149c414a2f311497eb7fe8cc13bf4970f1e5ce7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 21 Aug 2025 11:21:09 -0700
Subject: [PATCH 2/2] [RISCV] Use llvm_anyint_ty instead of llvm_any_type for
 scalar intrinsics. NFC

---
 llvm/include/llvm/IR/IntrinsicsRISCV.td | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 243100f0c7180..c74cc3c04833a 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -80,11 +80,11 @@ let TargetPrefix = "riscv" in {
 let TargetPrefix = "riscv" in {
 
   class BitManipGPRIntrinsics
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable]>;
   class BitManipGPRGPRIntrinsics
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable]>;
 
@@ -115,11 +115,11 @@ let TargetPrefix = "riscv" in {
 
   // Zimop
   def int_riscv_mopr
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
   def int_riscv_moprr
-      : DefaultAttrsIntrinsic<[llvm_any_ty],
+      : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
                               [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
 } // TargetPrefix = "riscv"
@@ -135,7 +135,7 @@ defvar NoScalarOperand = 0xF;
 defvar NoVLOperand = 0x1F;
 
 class RISCVVIntrinsic {
-  // These intrinsics may accept illegal integer values in their llvm_any_ty
+  // These intrinsics may accept illegal integer values in their llvm_anyint_ty
   // operand, so they have to be extended.
   Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
   bits<4> ScalarOperand = NoScalarOperand;