[llvm] [DAG] Constant fold ISD::FSHL/FSHR nodes (PR #154480)

[via llvm-commits]

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@@ -8158,6 +8180,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     }
     break;
   }
+  case ISD::FSHL:
+  case ISD::FSHR:
+    // Constant folding.
+    if (SDValue V = FoldConstantArithmetic(Opcode, DL, VT, {N1, N2, N3}))
+      return V;
+    break;
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XChy wrote:

Hmm, a quick try shows that some operators like `VECTOR_COMPRESS` cause the assertion in FoldConstantArithmetic. I will look into the reason later.

https://github.com/llvm/llvm-project/pull/154480