[llvm] dbadab9 - [GlobalISel] Support saturated truncate (#150219)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 21 07:37:57 PDT 2025
Author: jyli0116
Date: 2025-08-21T15:37:53+01:00
New Revision: dbadab96eb5c52f1f6fa6233aa084f3047873dc4
URL: https://github.com/llvm/llvm-project/commit/dbadab96eb5c52f1f6fa6233aa084f3047873dc4
DIFF: https://github.com/llvm/llvm-project/commit/dbadab96eb5c52f1f6fa6233aa084f3047873dc4.diff
LOG: [GlobalISel] Support saturated truncate (#150219)
Implements combining and legalization of G_TRUNC_SSAT_S, G_TRUNC_SSAT_U,
and G_TRUNC_USAT_U, which where previously added to SDAG with the below
patterns:
```
truncate(smin(smax(x, C1), C2)) -> trunc_ssat_s(x)
truncate(smax(smin(x, C2), C1)) -> trunc_ssat_s(x)
truncate(smax(smin(x, C), 0)) -> trunc_ssat_u(x)
truncate(smin(smax(x, 0), C)) -> trunc_ssat_u(x)
truncate(umin(smax(x, 0), C)) -> trunc_ssat_u(x)
truncate(umin(x, C)) -> trunc_usat_u(x)
```
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
llvm/include/llvm/Target/GlobalISel/Combine.td
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
llvm/test/CodeGen/AArch64/qmovn.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 15a5f82ac0567..6dba689e8af71 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -727,6 +727,23 @@ class CombinerHelper {
bool matchUMulHToLShr(MachineInstr &MI) const;
void applyUMulHToLShr(MachineInstr &MI) const;
+ // Combine trunc(smin(smax(x, C1), C2)) -> truncssat_s(x)
+ // or trunc(smax(smin(x, C2), C1)) -> truncssat_s(x).
+ bool matchTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
+ void applyTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
+
+ // Combine trunc(smin(smax(x, 0), C)) -> truncssat_u(x)
+ // or trunc(smax(smin(x, C), 0)) -> truncssat_u(x)
+ // or trunc(umin(smax(x, 0), C)) -> truncssat_u(x)
+ bool matchTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
+ void applyTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
+
+ // Combine trunc(umin(x, C)) -> truncusat_u(x).
+ bool matchTruncUSatU(MachineInstr &MI, MachineInstr &MinMI) const;
+
+ // Combine truncusat_u(fptoui(x)) -> fptoui_sat(x)
+ bool matchTruncUSatUToFPTOUISat(MachineInstr &MI, MachineInstr &SrcMI) const;
+
/// Try to transform \p MI by using all of the above
/// combine functions. Returns true if changed.
bool tryCombine(MachineInstr &MI) const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index 4292c0b31c750..5faf57fd06228 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -874,6 +874,9 @@ class GCastOp : public GenericMachineInstr {
case TargetOpcode::G_SEXT:
case TargetOpcode::G_SITOFP:
case TargetOpcode::G_TRUNC:
+ case TargetOpcode::G_TRUNC_SSAT_S:
+ case TargetOpcode::G_TRUNC_SSAT_U:
+ case TargetOpcode::G_TRUNC_USAT_U:
case TargetOpcode::G_UITOFP:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_ANYEXT:
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index a557743f684ca..9564b581c5ebb 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1250,6 +1250,35 @@ def mulh_to_lshr : GICombineRule<
def mulh_combines : GICombineGroup<[mulh_to_lshr]>;
+def trunc_ssats : GICombineRule<
+ (defs root:$root, register_matchinfo:$matchinfo),
+ (match (G_TRUNC $dst, $src):$root,
+ [{ return Helper.matchTruncSSatS(*${root}, ${matchinfo}); }]),
+ (apply [{ Helper.applyTruncSSatS(*${root}, ${matchinfo}); }])>;
+
+def trunc_ssatu : GICombineRule<
+ (defs root:$root, register_matchinfo:$matchinfo),
+ (match (G_TRUNC $dst, $src):$root,
+ [{ return Helper.matchTruncSSatU(*${root}, ${matchinfo}); }]),
+ (apply [{ Helper.applyTruncSSatU(*${root}, ${matchinfo}); }])>;
+
+def trunc_usatu : GICombineRule<
+ (defs root:$root),
+ (match (G_UMIN $min, $x, $y):$Min,
+ (G_TRUNC $dst, $min):$root,
+ [{ return Helper.matchTruncUSatU(*${root}, *${Min}); }]),
+ (apply (G_TRUNC_USAT_U $dst, $x))>;
+
+def truncusatu_to_fptouisat : GICombineRule<
+ (defs root:$root),
+ (match (G_FPTOUI $src, $x):$Src,
+ (G_TRUNC_USAT_U $dst, $src):$root,
+ [{ return Helper.matchTruncUSatUToFPTOUISat(*${root}, *${Src}); }]),
+ (apply (G_FPTOUI_SAT $dst, $x))
+>;
+
+def truncsat_combines : GICombineGroup<[trunc_ssats, trunc_ssatu, trunc_usatu, truncusatu_to_fptouisat]>;
+
def redundant_neg_operands: GICombineRule<
(defs root:$root, build_fn_matchinfo:$matchinfo),
(match (wip_match_opcode G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMAD, G_FMA):$root,
@@ -2074,7 +2103,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
simplify_neg_minmax, combine_concat_vector,
sext_trunc, zext_trunc, prefer_sign_combines, shuffle_combines,
- combine_use_vector_truncate, merge_combines, overflow_combines]>;
+ combine_use_vector_truncate, merge_combines, overflow_combines, truncsat_combines]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in
// this group have been selected based on experiments to balance code size and
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 8163dea4e31c0..0674f5fd1ae06 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -5924,6 +5924,96 @@ void CombinerHelper::applyUMulHToLShr(MachineInstr &MI) const {
MI.eraseFromParent();
}
+bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+ unsigned NumDstBits = DstTy.getScalarSizeInBits();
+ unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
+ assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
+
+ if (!LI || !isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}}))
+ return false;
+
+ APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
+ APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
+ return mi_match(Src, MRI,
+ m_GSMin(m_GSMax(m_Reg(MatchInfo),
+ m_SpecificICstOrSplat(SignedMin)),
+ m_SpecificICstOrSplat(SignedMax))) ||
+ mi_match(Src, MRI,
+ m_GSMax(m_GSMin(m_Reg(MatchInfo),
+ m_SpecificICstOrSplat(SignedMax)),
+ m_SpecificICstOrSplat(SignedMin)));
+}
+
+void CombinerHelper::applyTruncSSatS(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Builder.buildTruncSSatS(Dst, MatchInfo);
+ MI.eraseFromParent();
+}
+
+bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+ unsigned NumDstBits = DstTy.getScalarSizeInBits();
+ unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
+ assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
+
+ if (!LI || !isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}}))
+ return false;
+ APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
+ return mi_match(Src, MRI,
+ m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
+ m_SpecificICstOrSplat(UnsignedMax))) ||
+ mi_match(Src, MRI,
+ m_GSMax(m_GSMin(m_Reg(MatchInfo),
+ m_SpecificICstOrSplat(UnsignedMax)),
+ m_SpecificICstOrSplat(0))) ||
+ mi_match(Src, MRI,
+ m_GUMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
+ m_SpecificICstOrSplat(UnsignedMax)));
+}
+
+void CombinerHelper::applyTruncSSatU(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Builder.buildTruncSSatU(Dst, MatchInfo);
+ MI.eraseFromParent();
+}
+
+bool CombinerHelper::matchTruncUSatU(MachineInstr &MI,
+ MachineInstr &MinMI) const {
+ Register Min = MinMI.getOperand(2).getReg();
+ Register Val = MinMI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+ LLT SrcTy = MRI.getType(Val);
+ unsigned NumDstBits = DstTy.getScalarSizeInBits();
+ unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
+ assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
+
+ if (!LI || !isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}}))
+ return false;
+ APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
+ return mi_match(Min, MRI, m_SpecificICstOrSplat(UnsignedMax)) &&
+ !mi_match(Val, MRI, m_GSMax(m_Reg(), m_Reg()));
+}
+
+bool CombinerHelper::matchTruncUSatUToFPTOUISat(MachineInstr &MI,
+ MachineInstr &SrcMI) const {
+ LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+ LLT SrcTy = MRI.getType(SrcMI.getOperand(1).getReg());
+
+ return LI &&
+ isLegalOrBeforeLegalizer({TargetOpcode::G_FPTOUI_SAT, {DstTy, SrcTy}});
+}
+
bool CombinerHelper::matchRedundantNegOperands(MachineInstr &MI,
BuildFnTy &MatchInfo) const {
unsigned Opc = MI.getOpcode();
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 99f0af5f6a3f8..5f499e5e9700a 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -351,9 +351,10 @@ def AArch64PostLegalizerLowering
// Post-legalization combines which are primarily optimizations.
def AArch64PostLegalizerCombiner
: GICombiner<"AArch64PostLegalizerCombinerImpl",
- [copy_prop, cast_of_cast_combines, buildvector_of_truncate,
- integer_of_truncate, mutate_anyext_to_zext,
- combines_for_extload, combine_indexed_load_store, sext_trunc_sextload,
+ [copy_prop, cast_of_cast_combines,
+ buildvector_of_truncate, integer_of_truncate,
+ mutate_anyext_to_zext, combines_for_extload,
+ combine_indexed_load_store, sext_trunc_sextload,
hoist_logic_op_with_same_opcode_hands,
redundant_and, xor_of_and_with_same_reg,
extractvecelt_pairwise_add, redundant_or,
@@ -367,5 +368,6 @@ def AArch64PostLegalizerCombiner
select_to_minmax, or_to_bsp, combine_concat_vector,
commute_constant_to_rhs, extract_vec_elt_combines,
push_freeze_to_prevent_poison_from_propagating,
- combine_mul_cmlt, combine_use_vector_truncate, extmultomull]> {
+ combine_mul_cmlt, combine_use_vector_truncate,
+ extmultomull, truncsat_combines]> {
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index efc62ea8ff6c2..1f8bed6019952 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1847,11 +1847,11 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_sdot:
return LowerTriOp(AArch64::G_SDOT);
case Intrinsic::aarch64_neon_sqxtn:
- return LowerUnaryOp(AArch64::G_TRUNC_SSAT_S);
+ return LowerUnaryOp(TargetOpcode::G_TRUNC_SSAT_S);
case Intrinsic::aarch64_neon_sqxtun:
- return LowerUnaryOp(AArch64::G_TRUNC_SSAT_U);
+ return LowerUnaryOp(TargetOpcode::G_TRUNC_SSAT_U);
case Intrinsic::aarch64_neon_uqxtn:
- return LowerUnaryOp(AArch64::G_TRUNC_USAT_U);
+ return LowerUnaryOp(TargetOpcode::G_TRUNC_USAT_U);
case Intrinsic::vector_reverse:
// TODO: Add support for vector_reverse
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index d205b133fbe8c..b09a86723bb56 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -7,45 +7,11 @@
; i32 saturate
define <2 x i32> @stest_f64i32(<2 x double> %x) {
-; CHECK-CVT-SD-LABEL: stest_f64i32:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-SD-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: stest_f64i32:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: stest_f64i32:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-GI-NEXT: adrp x8, .LCPI0_1
-; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_1]
-; CHECK-CVT-GI-NEXT: adrp x8, .LCPI0_0
-; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-CVT-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
-; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: stest_f64i32:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: adrp x8, .LCPI0_1
-; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_1]
-; CHECK-FP16-GI-NEXT: adrp x8, .LCPI0_0
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: stest_f64i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>
@@ -103,39 +69,11 @@ entry:
}
define <2 x i32> @ustest_f64i32(<2 x double> %x) {
-; CHECK-CVT-SD-LABEL: ustest_f64i32:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-SD-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: ustest_f64i32:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: ustest_f64i32:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-CVT-GI-NEXT: cmgt v1.2d, v0.2d, #0
-; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: ustest_f64i32:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-FP16-GI-NEXT: cmgt v1.2d, v0.2d, #0
-; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: ustest_f64i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>
@@ -596,37 +534,11 @@ entry:
}
define <4 x i16> @stest_f32i16(<4 x float> %x) {
-; CHECK-CVT-SD-LABEL: stest_f32i16:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: stest_f32i16:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: stest_f32i16:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: stest_f32i16:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: stest_f32i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%0 = icmp slt <4 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767>
@@ -638,33 +550,11 @@ entry:
}
define <4 x i16> @utest_f32i16(<4 x float> %x) {
-; CHECK-CVT-SD-LABEL: utest_f32i16:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: utest_f32i16:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-FP16-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: utest_f32i16:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: utest_f32i16:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: utest_f32i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i32>
%0 = icmp ult <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -674,37 +564,11 @@ entry:
}
define <4 x i16> @ustest_f32i16(<4 x float> %x) {
-; CHECK-CVT-SD-LABEL: ustest_f32i16:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: ustest_f32i16:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-SD-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: ustest_f32i16:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v2.4s
-; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: ustest_f32i16:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v2.4s
-; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: ustest_f32i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%0 = icmp slt <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -716,49 +580,29 @@ entry:
}
define <8 x i16> @stest_f16i16(<8 x half> %x) {
-; CHECK-CVT-SD-LABEL: stest_f16i16:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
-; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
-; CHECK-CVT-SD-NEXT: ret
+; CHECK-CVT-LABEL: stest_f16i16:
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: stest_f16i16:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-CVT-GI-LABEL: stest_f16i16:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: smax v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-CVT-GI-NEXT: ret
-;
; CHECK-FP16-GI-LABEL: stest_f16i16:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: smax v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-FP16-GI-NEXT: sqxtn2 v0.8h, v2.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
@@ -771,43 +615,29 @@ entry:
}
define <8 x i16> @utesth_f16i16(<8 x half> %x) {
-; CHECK-CVT-SD-LABEL: utesth_f16i16:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
-; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
-; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
-; CHECK-CVT-SD-NEXT: ret
+; CHECK-CVT-LABEL: utesth_f16i16:
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i16:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-CVT-GI-LABEL: utesth_f16i16:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: fcvtzu v2.4s, v2.4s
-; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: umin v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-CVT-GI-NEXT: ret
-;
; CHECK-FP16-GI-LABEL: utesth_f16i16:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: umin v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-FP16-GI-NEXT: uqxtn2 v0.8h, v2.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <8 x half> %x to <8 x i32>
@@ -818,49 +648,29 @@ entry:
}
define <8 x i16> @ustest_f16i16(<8 x half> %x) {
-; CHECK-CVT-SD-LABEL: ustest_f16i16:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
-; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
-; CHECK-CVT-SD-NEXT: ret
+; CHECK-CVT-LABEL: ustest_f16i16:
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: ustest_f16i16:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-CVT-GI-LABEL: ustest_f16i16:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smax v1.4s, v2.4s, v3.4s
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v3.4s
-; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
-; CHECK-CVT-GI-NEXT: ret
-;
; CHECK-FP16-GI-LABEL: ustest_f16i16:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smax v1.4s, v2.4s, v3.4s
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v3.4s
-; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-FP16-GI-NEXT: sqxtun2 v0.8h, v2.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
@@ -2195,45 +2005,11 @@ entry:
; i32 saturate
define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
-; CHECK-CVT-SD-LABEL: stest_f64i32_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-SD-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: stest_f64i32_mm:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: stest_f64i32_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-GI-NEXT: adrp x8, .LCPI27_1
-; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_1]
-; CHECK-CVT-GI-NEXT: adrp x8, .LCPI27_0
-; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_0]
-; CHECK-CVT-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
-; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: stest_f64i32_mm:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: adrp x8, .LCPI27_1
-; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_1]
-; CHECK-FP16-GI-NEXT: adrp x8, .LCPI27_0
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_0]
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: stest_f64i32_mm:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)
@@ -2288,39 +2064,11 @@ entry:
}
define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
-; CHECK-CVT-SD-LABEL: ustest_f64i32_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-SD-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: ustest_f64i32_mm:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: ustest_f64i32_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-CVT-GI-NEXT: cmgt v1.2d, v0.2d, #0
-; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: ustest_f64i32_mm:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-FP16-GI-NEXT: cmgt v1.2d, v0.2d, #0
-; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: ustest_f64i32_mm:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -2764,37 +2512,11 @@ entry:
}
define <4 x i16> @stest_f32i16_mm(<4 x float> %x) {
-; CHECK-CVT-SD-LABEL: stest_f32i16_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: stest_f32i16_mm:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: stest_f32i16_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: stest_f32i16_mm:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: stest_f32i16_mm:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
@@ -2804,33 +2526,11 @@ entry:
}
define <4 x i16> @utest_f32i16_mm(<4 x float> %x) {
-; CHECK-CVT-SD-LABEL: utest_f32i16_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: utest_f32i16_mm:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-FP16-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: utest_f32i16_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: utest_f32i16_mm:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: utest_f32i16_mm:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i32>
%spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -2839,37 +2539,11 @@ entry:
}
define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
-; CHECK-CVT-SD-LABEL: ustest_f32i16_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-CVT-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: ustest_f32i16_mm:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-SD-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-CVT-GI-LABEL: ustest_f32i16_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v2.4s
-; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-CVT-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: ustest_f32i16_mm:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v2.4s
-; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: ustest_f32i16_mm:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -2879,49 +2553,29 @@ entry:
}
define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-SD-LABEL: stest_f16i16_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
-; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
-; CHECK-CVT-SD-NEXT: ret
+; CHECK-CVT-LABEL: stest_f16i16_mm:
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: stest_f16i16_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-CVT-GI-LABEL: stest_f16i16_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-CVT-GI-NEXT: smax v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-CVT-GI-NEXT: ret
-;
; CHECK-FP16-GI-LABEL: stest_f16i16_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-FP16-GI-NEXT: smax v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-FP16-GI-NEXT: sqxtn2 v0.8h, v2.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
@@ -2932,43 +2586,29 @@ entry:
}
define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-SD-LABEL: utesth_f16i16_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
-; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
-; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
-; CHECK-CVT-SD-NEXT: ret
+; CHECK-CVT-LABEL: utesth_f16i16_mm:
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i16_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-CVT-GI-LABEL: utesth_f16i16_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: fcvtzu v2.4s, v2.4s
-; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: umin v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-CVT-GI-NEXT: ret
-;
; CHECK-FP16-GI-LABEL: utesth_f16i16_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: umin v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-FP16-GI-NEXT: uqxtn2 v0.8h, v2.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <8 x half> %x to <8 x i32>
@@ -2978,49 +2618,29 @@ entry:
}
define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-SD-LABEL: ustest_f16i16_mm:
-; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
-; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
-; CHECK-CVT-SD-NEXT: ret
+; CHECK-CVT-LABEL: ustest_f16i16_mm:
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: ustest_f16i16_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-CVT-GI-LABEL: ustest_f16i16_mm:
-; CHECK-CVT-GI: // %bb.0: // %entry
-; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
-; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-CVT-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-CVT-GI-NEXT: smax v1.4s, v2.4s, v3.4s
-; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v3.4s
-; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
-; CHECK-CVT-GI-NEXT: ret
-;
; CHECK-FP16-GI-LABEL: ustest_f16i16_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-FP16-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-FP16-GI-NEXT: smax v1.4s, v2.4s, v3.4s
-; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v3.4s
-; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
+; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-FP16-GI-NEXT: sqxtun2 v0.8h, v2.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
@@ -4340,5 +3960,4 @@ declare <2 x i128> @llvm.smin.v2i128(<2 x i128>, <2 x i128>)
declare <2 x i128> @llvm.smax.v2i128(<2 x i128>, <2 x i128>)
declare <2 x i128> @llvm.umin.v2i128(<2 x i128>, <2 x i128>)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-CVT: {{.*}}
; CHECK-FP16: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index e580191ecc55e..c74112937ba53 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -1837,21 +1837,11 @@ define <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
}
define <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
-; CHECK-SD-LABEL: test_signed_v4f32_v4i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_signed_v4f32_v4i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x
}
@@ -2949,28 +2939,17 @@ define <4 x i13> @test_signed_v4f16_v4i13(<4 x half> %f) {
}
define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_signed_v4f16_v4i16:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-SD-CVT-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-SD-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_signed_v4f16_v4i16:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: test_signed_v4f16_v4i16:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h
; CHECK-FP16-NEXT: ret
-;
-; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i16:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-CVT-NEXT: ret
%x = call <4 x i16> @llvm.fptosi.sat.v4f16.v4i16(<4 x half> %f)
ret <4 x i16> %x
}
@@ -3489,11 +3468,11 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_signed_v8f16_v8i8:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: sqxtn v0.8b, v0.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v8f16_v8i8:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i8:
; CHECK-GI-CVT: // %bb.0:
@@ -3510,16 +3489,6 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i8:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v1.8h, #127
-; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: mvni v2.8h, #127
-; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
}
@@ -3585,17 +3554,12 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: smax v2.4s, v2.4s, v1.4s
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-GI-CVT-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-GI-CVT-NEXT: sqxtn2 v0.8h, v2.4s
; CHECK-GI-CVT-NEXT: ret
%x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x
@@ -4430,26 +4394,13 @@ define <16 x i8> @test_signed_v16f32_v16i8(<16 x float> %f) {
}
define <8 x i16> @test_signed_v8f32_v8i16(<8 x float> %f) {
-; CHECK-SD-LABEL: test_signed_v8f32_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-SD-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: sqxtn2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_signed_v8f32_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.4s, #127, msl #8
-; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: mvni v2.4s, #127, msl #8
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_signed_v8f32_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
+; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptosi.sat.v8f32.v8i16(<8 x float> %f)
ret <8 x i16> %x
}
@@ -4469,22 +4420,14 @@ define <16 x i16> @test_signed_v16f32_v16i16(<16 x float> %f) {
;
; CHECK-GI-LABEL: test_signed_v16f32_v16i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v4.4s, #127, msl #8
; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-GI-NEXT: fcvtzs v4.4s, v1.4s
; CHECK-GI-NEXT: fcvtzs v3.4s, v3.4s
-; CHECK-GI-NEXT: mvni v5.4s, #127, msl #8
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: smin v1.4s, v1.4s, v4.4s
-; CHECK-GI-NEXT: smin v2.4s, v2.4s, v4.4s
-; CHECK-GI-NEXT: smin v3.4s, v3.4s, v4.4s
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v5.4s
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v5.4s
-; CHECK-GI-NEXT: smax v2.4s, v2.4s, v5.4s
-; CHECK-GI-NEXT: smax v3.4s, v3.4s, v5.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: uzp1 v1.8h, v2.8h, v3.8h
+; CHECK-GI-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-GI-NEXT: sqxtn v1.4h, v2.4s
+; CHECK-GI-NEXT: sqxtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: sqxtn2 v1.8h, v3.4s
; CHECK-GI-NEXT: ret
%x = call <16 x i16> @llvm.fptosi.sat.v16f32.v16i16(<16 x float> %f)
ret <16 x i16> %x
@@ -4518,13 +4461,13 @@ define <16 x i8> @test_signed_v16f16_v16i8(<16 x half> %f) {
; CHECK-SD-CVT-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_signed_v16f16_v16i8:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: fcvtzs v1.8h, v1.8h
-; CHECK-SD-FP16-NEXT: sqxtn v0.8b, v0.8h
-; CHECK-SD-FP16-NEXT: sqxtn2 v0.16b, v1.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v16f16_v16i8:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: fcvtzs v1.8h, v1.8h
+; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: sqxtn2 v0.16b, v1.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_signed_v16f16_v16i8:
; CHECK-GI-CVT: // %bb.0:
@@ -4550,19 +4493,6 @@ define <16 x i8> @test_signed_v16f16_v16i8(<16 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v3.8h, v1.8h
; CHECK-GI-CVT-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v16f16_v16i8:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v2.8h, #127
-; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: fcvtzs v1.8h, v1.8h
-; CHECK-GI-FP16-NEXT: mvni v3.8h, #127
-; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: smin v1.8h, v1.8h, v2.8h
-; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v3.8h
-; CHECK-GI-FP16-NEXT: smax v1.8h, v1.8h, v3.8h
-; CHECK-GI-FP16-NEXT: uzp1 v0.16b, v0.16b, v1.16b
-; CHECK-GI-FP16-NEXT: ret
%x = call <16 x i8> @llvm.fptosi.sat.v16f16.v16i8(<16 x half> %f)
ret <16 x i8> %x
}
@@ -4592,26 +4522,18 @@ define <16 x i16> @test_signed_v16f16_v16i16(<16 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_signed_v16f16_v16i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: fcvtl v4.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-GI-CVT-NEXT: movi v2.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: mvni v5.4s, #127, msl #8
+; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v2.4s
; CHECK-GI-CVT-NEXT: fcvtzs v3.4s, v3.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v4.4s, v4.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-GI-CVT-NEXT: smin v3.4s, v3.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smin v4.4s, v4.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smax v2.4s, v3.4s, v5.4s
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v5.4s
-; CHECK-GI-CVT-NEXT: smax v3.4s, v4.4s, v5.4s
-; CHECK-GI-CVT-NEXT: smax v1.4s, v1.4s, v5.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v3.8h, v1.8h
+; CHECK-GI-CVT-NEXT: fcvtzs v4.4s, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzs v5.4s, v1.4s
+; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v2.4s
+; CHECK-GI-CVT-NEXT: sqxtn v1.4h, v3.4s
+; CHECK-GI-CVT-NEXT: sqxtn2 v0.8h, v4.4s
+; CHECK-GI-CVT-NEXT: sqxtn2 v1.8h, v5.4s
; CHECK-GI-CVT-NEXT: ret
%x = call <16 x i16> @llvm.fptosi.sat.v16f16.v16i16(<16 x half> %f)
ret <16 x i16> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 4053d56b88545..efe0a1bedbc9e 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -1528,19 +1528,11 @@ define <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) {
}
define <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) {
-; CHECK-SD-LABEL: test_unsigned_v4f32_v4i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_unsigned_v4f32_v4i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x
}
@@ -2385,26 +2377,17 @@ define <4 x i13> @test_unsigned_v4f16_v4i13(<4 x half> %f) {
}
define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i16:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-CVT-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-SD-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i16:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i16:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h
; CHECK-FP16-NEXT: ret
-;
-; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i16:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-CVT-NEXT: ret
%x = call <4 x i16> @llvm.fptoui.sat.v4f16.v4i16(<4 x half> %f)
ret <4 x i16> %x
}
@@ -2850,11 +2833,11 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i8:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: uqxtn v0.8b, v0.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i8:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: uqxtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i8:
; CHECK-GI-CVT: // %bb.0:
@@ -2868,14 +2851,6 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i8:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v1.2d, #0xff00ff00ff00ff
-; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
}
@@ -2933,14 +2908,12 @@ define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-GI-CVT-NEXT: fcvtzu v2.4s, v2.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: umin v2.4s, v2.4s, v1.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-GI-CVT-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-GI-CVT-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-GI-CVT-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-GI-CVT-NEXT: uqxtn2 v0.8h, v2.4s
; CHECK-GI-CVT-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x
@@ -3653,23 +3626,13 @@ define <16 x i8> @test_unsigned_v16f32_v16i8(<16 x float> %f) {
}
define <8 x i16> @test_unsigned_v8f32_v8i16(<8 x float> %f) {
-; CHECK-SD-LABEL: test_unsigned_v8f32_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: uqxtn2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_unsigned_v8f32_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-GI-NEXT: umin v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: umin v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_unsigned_v8f32_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: uqxtn2 v0.8h, v1.4s
+; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f32.v8i16(<8 x float> %f)
ret <8 x i16> %x
}
@@ -3689,17 +3652,14 @@ define <16 x i16> @test_unsigned_v16f32_v16i16(<16 x float> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v16f32_v16i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v4.2d, #0x00ffff0000ffff
; CHECK-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-GI-NEXT: fcvtzu v2.4s, v2.4s
+; CHECK-GI-NEXT: fcvtzu v4.4s, v1.4s
; CHECK-GI-NEXT: fcvtzu v3.4s, v3.4s
-; CHECK-GI-NEXT: umin v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: umin v1.4s, v1.4s, v4.4s
-; CHECK-GI-NEXT: umin v2.4s, v2.4s, v4.4s
-; CHECK-GI-NEXT: umin v3.4s, v3.4s, v4.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: uzp1 v1.8h, v2.8h, v3.8h
+; CHECK-GI-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-GI-NEXT: uqxtn v1.4h, v2.4s
+; CHECK-GI-NEXT: uqxtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: uqxtn2 v1.8h, v3.4s
; CHECK-GI-NEXT: ret
%x = call <16 x i16> @llvm.fptoui.sat.v16f32.v16i16(<16 x float> %f)
ret <16 x i16> %x
@@ -3728,13 +3688,13 @@ define <16 x i8> @test_unsigned_v16f16_v16i8(<16 x half> %f) {
; CHECK-SD-CVT-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v16f16_v16i8:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: fcvtzu v1.8h, v1.8h
-; CHECK-SD-FP16-NEXT: uqxtn v0.8b, v0.8h
-; CHECK-SD-FP16-NEXT: uqxtn2 v0.16b, v1.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i8:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: fcvtzu v1.8h, v1.8h
+; CHECK-FP16-NEXT: uqxtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: uqxtn2 v0.16b, v1.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_v16f16_v16i8:
; CHECK-GI-CVT: // %bb.0:
@@ -3755,16 +3715,6 @@ define <16 x i8> @test_unsigned_v16f16_v16i8(<16 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v4.8h, v1.8h
; CHECK-GI-CVT-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v16f16_v16i8:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v2.2d, #0xff00ff00ff00ff
-; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: fcvtzu v1.8h, v1.8h
-; CHECK-GI-FP16-NEXT: umin v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: umin v1.8h, v1.8h, v2.8h
-; CHECK-GI-FP16-NEXT: uzp1 v0.16b, v0.16b, v1.16b
-; CHECK-GI-FP16-NEXT: ret
%x = call <16 x i8> @llvm.fptoui.sat.v16f16.v16i8(<16 x half> %f)
ret <16 x i8> %x
}
@@ -3794,21 +3744,18 @@ define <16 x i16> @test_unsigned_v16f16_v16i16(<16 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_unsigned_v16f16_v16i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: fcvtl v4.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-GI-CVT-NEXT: movi v2.2d, #0x00ffff0000ffff
+; CHECK-GI-CVT-NEXT: fcvtzu v2.4s, v2.4s
; CHECK-GI-CVT-NEXT: fcvtzu v3.4s, v3.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v4.4s, v4.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-GI-CVT-NEXT: umin v3.4s, v3.4s, v2.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v2.4s
-; CHECK-GI-CVT-NEXT: umin v4.4s, v4.4s, v2.4s
-; CHECK-GI-CVT-NEXT: umin v1.4s, v1.4s, v2.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v3.8h, v0.8h
-; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v4.8h, v1.8h
+; CHECK-GI-CVT-NEXT: fcvtzu v4.4s, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzu v5.4s, v1.4s
+; CHECK-GI-CVT-NEXT: uqxtn v0.4h, v2.4s
+; CHECK-GI-CVT-NEXT: uqxtn v1.4h, v3.4s
+; CHECK-GI-CVT-NEXT: uqxtn2 v0.8h, v4.4s
+; CHECK-GI-CVT-NEXT: uqxtn2 v1.8h, v5.4s
; CHECK-GI-CVT-NEXT: ret
%x = call <16 x i16> @llvm.fptoui.sat.v16f16.v16i16(<16 x half> %f)
ret <16 x i16> %x
diff --git a/llvm/test/CodeGen/AArch64/qmovn.ll b/llvm/test/CodeGen/AArch64/qmovn.ll
index d24af25903326..bd99c1ca81d3a 100644
--- a/llvm/test/CodeGen/AArch64/qmovn.ll
+++ b/llvm/test/CodeGen/AArch64/qmovn.ll
@@ -3,19 +3,10 @@
; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs -global-isel=1 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i16> @vqmovni32_smaxmin(<4 x i32> %s0) {
-; CHECK-SD-LABEL: vqmovni32_smaxmin:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni32_smaxmin:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni32_smaxmin:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
@@ -26,19 +17,10 @@ entry:
}
define <4 x i16> @vqmovni32_sminmax(<4 x i32> %s0) {
-; CHECK-SD-LABEL: vqmovni32_sminmax:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni32_sminmax:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-NEXT: movi v2.4s, #127, msl #8
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni32_sminmax:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
@@ -49,17 +31,10 @@ entry:
}
define <4 x i16> @vqmovni32_umaxmin(<4 x i32> %s0) {
-; CHECK-SD-LABEL: vqmovni32_umaxmin:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni32_umaxmin:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni32_umaxmin:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -68,19 +43,10 @@ entry:
}
define <8 x i8> @vqmovni16_smaxmin(<8 x i16> %s0) {
-; CHECK-SD-LABEL: vqmovni16_smaxmin:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni16_smaxmin:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.8h, #127
-; CHECK-GI-NEXT: mvni v2.8h, #127
-; CHECK-GI-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni16_smaxmin:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.8b, v0.8h
+; CHECK-NEXT: ret
entry:
%c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
@@ -91,19 +57,10 @@ entry:
}
define <8 x i8> @vqmovni16_sminmax(<8 x i16> %s0) {
-; CHECK-SD-LABEL: vqmovni16_sminmax:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni16_sminmax:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mvni v1.8h, #127
-; CHECK-GI-NEXT: movi v2.8h, #127
-; CHECK-GI-NEXT: smax v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: smin v0.8h, v0.8h, v2.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni16_sminmax:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.8b, v0.8h
+; CHECK-NEXT: ret
entry:
%c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
@@ -114,17 +71,10 @@ entry:
}
define <8 x i8> @vqmovni16_umaxmin(<8 x i16> %s0) {
-; CHECK-SD-LABEL: vqmovni16_umaxmin:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: uqxtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni16_umaxmin:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
-; CHECK-GI-NEXT: umin v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni16_umaxmin:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uqxtn v0.8b, v0.8h
+; CHECK-NEXT: ret
entry:
%c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
@@ -133,23 +83,10 @@ entry:
}
define <2 x i32> @vqmovni64_smaxmin(<2 x i64> %s0) {
-; CHECK-SD-LABEL: vqmovni64_smaxmin:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni64_smaxmin:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: adrp x8, .LCPI6_1
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI6_1]
-; CHECK-GI-NEXT: adrp x8, .LCPI6_0
-; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
-; CHECK-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni64_smaxmin:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>
@@ -160,23 +97,10 @@ entry:
}
define <2 x i32> @vqmovni64_sminmax(<2 x i64> %s0) {
-; CHECK-SD-LABEL: vqmovni64_sminmax:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni64_sminmax:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: adrp x8, .LCPI7_1
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI7_1]
-; CHECK-GI-NEXT: adrp x8, .LCPI7_0
-; CHECK-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
-; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni64_sminmax:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>
@@ -187,20 +111,10 @@ entry:
}
define <2 x i32> @vqmovni64_smaxmin_u(<2 x i64> %s0) {
-; CHECK-SD-LABEL: vqmovni64_smaxmin_u:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni64_smaxmin_u:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, #0
-; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni64_smaxmin_u:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%c1 = icmp slt <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
@@ -211,20 +125,10 @@ entry:
}
define <2 x i32> @vqmovni64_sminmax_u(<2 x i64> %s0) {
-; CHECK-SD-LABEL: vqmovni64_sminmax_u:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni64_sminmax_u:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, #0
-; CHECK-GI-NEXT: movi v2.2d, #0x000000ffffffff
-; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: cmgt v1.2d, v2.2d, v0.2d
-; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni64_sminmax_u:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%c1 = icmp sgt <2 x i64> %s0, zeroinitializer
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> zeroinitializer
@@ -235,19 +139,10 @@ entry:
}
define <4 x i16> @vqmovni32_smaxmin_u(<4 x i32> %s0) {
-; CHECK-SD-LABEL: vqmovni32_smaxmin_u:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni32_smaxmin_u:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni32_smaxmin_u:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%c1 = icmp slt <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -258,19 +153,10 @@ entry:
}
define <4 x i16> @vqmovni32_sminmax_u(<4 x i32> %s0) {
-; CHECK-SD-LABEL: vqmovni32_sminmax_u:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni32_sminmax_u:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: movi v2.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni32_sminmax_u:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-NEXT: ret
entry:
%c1 = icmp sgt <4 x i32> %s0, zeroinitializer
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> zeroinitializer
@@ -281,19 +167,10 @@ entry:
}
define <8 x i8> @vqmovni16_smaxmin_u(<8 x i16> %s0) {
-; CHECK-SD-LABEL: vqmovni16_smaxmin_u:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtun v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni16_smaxmin_u:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-GI-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni16_smaxmin_u:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.8b, v0.8h
+; CHECK-NEXT: ret
entry:
%c1 = icmp slt <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
@@ -304,19 +181,10 @@ entry:
}
define <8 x i8> @vqmovni16_sminmax_u(<8 x i16> %s0) {
-; CHECK-SD-LABEL: vqmovni16_sminmax_u:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sqxtun v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni16_sminmax_u:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff
-; CHECK-GI-NEXT: smax v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: smin v0.8h, v0.8h, v2.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni16_sminmax_u:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.8b, v0.8h
+; CHECK-NEXT: ret
entry:
%c1 = icmp sgt <8 x i16> %s0, zeroinitializer
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> zeroinitializer
@@ -327,18 +195,10 @@ entry:
}
define <2 x i32> @vqmovni64_umaxmin(<2 x i64> %s0) {
-; CHECK-SD-LABEL: vqmovni64_umaxmin:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: uqxtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vqmovni64_umaxmin:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
-; CHECK-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vqmovni64_umaxmin:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uqxtn v0.2s, v0.2d
+; CHECK-NEXT: ret
entry:
%c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
@@ -349,21 +209,11 @@ entry:
; Test the (concat_vectors (X), (trunc(smin(smax(Y, -2^n), 2^n-1))) pattern.
define <16 x i8> @signed_minmax_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-SD-LABEL: signed_minmax_v8i16_to_v16i8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtn2 v0.16b, v1.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: signed_minmax_v8i16_to_v16i8:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.8h, #127
-; CHECK-GI-NEXT: mvni v3.8h, #127
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smin v1.8h, v1.8h, v2.8h
-; CHECK-GI-NEXT: smax v1.8h, v1.8h, v3.8h
-; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: signed_minmax_v8i16_to_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtn2 v0.16b, v1.8h
+; CHECK-NEXT: ret
entry:
%min = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %y, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)
%max = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %min, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)
@@ -373,21 +223,11 @@ entry:
}
define <8 x i16> @signed_minmax_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-SD-LABEL: signed_minmax_v4i32_to_v8i16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtn2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: signed_minmax_v4i32_to_v8i16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.4s, #127, msl #8
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: mvni v2.4s, #127, msl #8
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: signed_minmax_v4i32_to_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
+; CHECK-NEXT: ret
entry:
%min = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %y, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
%max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %min, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
@@ -397,25 +237,11 @@ entry:
}
define <4 x i32> @signed_minmax_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-SD-LABEL: signed_minmax_v2i64_to_v4i32:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtn2 v0.4s, v1.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: signed_minmax_v2i64_to_v4i32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: adrp x8, .LCPI17_1
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI17_1]
-; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
-; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI17_0]
-; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: signed_minmax_v2i64_to_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtn2 v0.4s, v1.2d
+; CHECK-NEXT: ret
entry:
%min = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %y, <2 x i64> <i64 2147483647, i64 2147483647>)
%max = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %min, <2 x i64> <i64 -2147483648, i64 -2147483648>)
@@ -427,21 +253,11 @@ entry:
; Test the (concat_vectors (X), (trunc(smax(smin(Y, 2^n-1), -2^n))) pattern.
define <16 x i8> @signed_maxmin_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-SD-LABEL: signed_maxmin_v8i16_to_v16i8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtn2 v0.16b, v1.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: signed_maxmin_v8i16_to_v16i8:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mvni v2.8h, #127
-; CHECK-GI-NEXT: movi v3.8h, #127
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smax v1.8h, v1.8h, v2.8h
-; CHECK-GI-NEXT: smin v1.8h, v1.8h, v3.8h
-; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: signed_maxmin_v8i16_to_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtn2 v0.16b, v1.8h
+; CHECK-NEXT: ret
entry:
%max = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %y, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)
%min = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %max, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)
@@ -451,21 +267,11 @@ entry:
}
define <8 x i16> @signed_maxmin_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-SD-LABEL: signed_maxmin_v4i32_to_v8i16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtn2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: signed_maxmin_v4i32_to_v8i16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mvni v2.4s, #127, msl #8
-; CHECK-GI-NEXT: movi v3.4s, #127, msl #8
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
-; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: signed_maxmin_v4i32_to_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
+; CHECK-NEXT: ret
entry:
%max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
%min = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %max, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
@@ -475,25 +281,11 @@ entry:
}
define <4 x i32> @signed_maxmin_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-SD-LABEL: signed_maxmin_v2i64_to_v4i32:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtn2 v0.4s, v1.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: signed_maxmin_v2i64_to_v4i32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: adrp x8, .LCPI20_1
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI20_1]
-; CHECK-GI-NEXT: adrp x8, .LCPI20_0
-; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI20_0]
-; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
-; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: signed_maxmin_v2i64_to_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtn2 v0.4s, v1.2d
+; CHECK-NEXT: ret
entry:
%max = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> <i64 -2147483648, i64 -2147483648>)
%min = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %max, <2 x i64> <i64 2147483647, i64 2147483647>)
@@ -505,19 +297,11 @@ entry:
; Test the (concat_vectors (X), (trunc(umin(Y, 2^n)))) pattern.
define <16 x i8> @unsigned_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-SD-LABEL: unsigned_v8i16_to_v16i8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: uqxtn2 v0.16b, v1.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: unsigned_v8i16_to_v16i8:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: umin v1.8h, v1.8h, v2.8h
-; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: unsigned_v8i16_to_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: uqxtn2 v0.16b, v1.8h
+; CHECK-NEXT: ret
entry:
%min = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %y, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
%trunc = trunc <8 x i16> %min to <8 x i8>
@@ -526,19 +310,11 @@ entry:
}
define <8 x i16> @unsigned_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-SD-LABEL: unsigned_v4i32_to_v8i16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: uqxtn2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: unsigned_v4i32_to_v8i16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: umin v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: unsigned_v4i32_to_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: uqxtn2 v0.8h, v1.4s
+; CHECK-NEXT: ret
entry:
%min = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %y, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
%trunc = trunc <4 x i32> %min to <4 x i16>
@@ -547,20 +323,11 @@ entry:
}
define <4 x i32> @unsigned_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-SD-LABEL: unsigned_v2i64_to_v4i32:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: uqxtn2 v0.4s, v1.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: unsigned_v2i64_to_v4i32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.2d, #0x000000ffffffff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: cmhi v3.2d, v2.2d, v1.2d
-; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: unsigned_v2i64_to_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: uqxtn2 v0.4s, v1.2d
+; CHECK-NEXT: ret
entry:
%min = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %y, <2 x i64> <i64 4294967295, i64 4294967295>)
%trunc = trunc <2 x i64> %min to <2 x i32>
@@ -571,21 +338,11 @@ entry:
; Test the (concat_vectors (X), (trunc(umin(smax(Y, 0), 2^n))))) pattern.
define <16 x i8> @us_maxmin_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-SD-LABEL: us_maxmin_v8i16_to_v16i8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtun2 v0.16b, v1.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: us_maxmin_v8i16_to_v16i8:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-GI-NEXT: movi v3.2d, #0xff00ff00ff00ff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smax v1.8h, v1.8h, v2.8h
-; CHECK-GI-NEXT: umin v1.8h, v1.8h, v3.8h
-; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: us_maxmin_v8i16_to_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtun2 v0.16b, v1.8h
+; CHECK-NEXT: ret
entry:
%max = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %y, <8 x i16> zeroinitializer)
%min = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %max, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
@@ -595,21 +352,11 @@ entry:
}
define <8 x i16> @us_maxmin_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-SD-LABEL: us_maxmin_v4i32_to_v8i16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtun2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: us_maxmin_v4i32_to_v8i16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-GI-NEXT: movi v3.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: umin v1.4s, v1.4s, v3.4s
-; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: us_maxmin_v4i32_to_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtun2 v0.8h, v1.4s
+; CHECK-NEXT: ret
entry:
%max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> zeroinitializer)
%min = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %max, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -619,22 +366,11 @@ entry:
}
define <4 x i32> @us_maxmin_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-SD-LABEL: us_maxmin_v2i64_to_v4i32:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtun2 v0.4s, v1.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: us_maxmin_v2i64_to_v4i32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, #0
-; CHECK-GI-NEXT: movi v3.2d, #0x000000ffffffff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: cmhi v2.2d, v3.2d, v1.2d
-; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
-; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: us_maxmin_v2i64_to_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtun2 v0.4s, v1.2d
+; CHECK-NEXT: ret
entry:
%max = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> zeroinitializer)
%min = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %max, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -646,21 +382,11 @@ entry:
; Test the (concat_vectors (X), (trunc(smin(smax(Y, 0), 2^n))))) pattern.
define <16 x i8> @sminsmax_range_unsigned_i16_to_i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-SD-LABEL: sminsmax_range_unsigned_i16_to_i8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtun2 v0.16b, v1.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: sminsmax_range_unsigned_i16_to_i8:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-GI-NEXT: movi v3.2d, #0xff00ff00ff00ff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smax v1.8h, v1.8h, v2.8h
-; CHECK-GI-NEXT: smin v1.8h, v1.8h, v3.8h
-; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: sminsmax_range_unsigned_i16_to_i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtun2 v0.16b, v1.8h
+; CHECK-NEXT: ret
entry:
%min = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %y, <8 x i16> zeroinitializer)
%max = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %min, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
@@ -670,21 +396,11 @@ entry:
}
define <8 x i16> @sminsmax_range_unsigned_i32_to_i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-SD-LABEL: sminsmax_range_unsigned_i32_to_i16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtun2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: sminsmax_range_unsigned_i32_to_i16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
-; CHECK-GI-NEXT: movi v3.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
-; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: sminsmax_range_unsigned_i32_to_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtun2 v0.8h, v1.4s
+; CHECK-NEXT: ret
entry:
%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> zeroinitializer)
%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %smax, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -694,22 +410,11 @@ entry:
}
define <4 x i32> @sminsmax_range_unsigned_i64_to_i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-SD-LABEL: sminsmax_range_unsigned_i64_to_i32:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: sqxtun2 v0.4s, v1.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: sminsmax_range_unsigned_i64_to_i32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, #0
-; CHECK-GI-NEXT: movi v3.2d, #0x000000ffffffff
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: cmgt v2.2d, v3.2d, v1.2d
-; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
-; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: sminsmax_range_unsigned_i64_to_i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: sqxtun2 v0.4s, v1.2d
+; CHECK-NEXT: ret
entry:
%smax = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> zeroinitializer)
%smin = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %smax, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -914,5 +619,3 @@ entry:
%shuffle = shufflevector <4 x i8> %x, <4 x i8> %trunc, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %shuffle
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
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