[llvm] [LivePhysRegs] Make use of `MBB.liveouts()` (semi-NFC) (PR #154728)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-regalloc

Author: Benjamin Maxwell (MacDue)

<details>
<summary>Changes</summary>

This is done for consistency with LiveRegUnits (see #<!-- -->154325). This is technically not an NFC, as `MBB.liveouts()` excludes runtime-defined liveins, but no users currently depend on this.

---
Full diff: https://github.com/llvm/llvm-project/pull/154728.diff


3 Files Affected:

- (modified) llvm/include/llvm/CodeGen/LivePhysRegs.h (+7) 
- (modified) llvm/lib/CodeGen/LivePhysRegs.cpp (+29-20) 
- (modified) llvm/lib/CodeGen/LiveRegUnits.cpp (+2-2) 


``````````diff
diff --git a/llvm/include/llvm/CodeGen/LivePhysRegs.h b/llvm/include/llvm/CodeGen/LivePhysRegs.h
index 2a719571fde2d..4af5b00014cb7 100644
--- a/llvm/include/llvm/CodeGen/LivePhysRegs.h
+++ b/llvm/include/llvm/CodeGen/LivePhysRegs.h
@@ -165,10 +165,17 @@ class LivePhysRegs {
   void dump() const;
 
 private:
+  /// Adds a register, taking the lane mask into consideration.
+  void addRegMaskPair(const MachineBasicBlock::RegisterMaskPair &Pair);
+
   /// Adds live-in registers from basic block \p MBB, taking associated
   /// lane masks into consideration.
   void addBlockLiveIns(const MachineBasicBlock &MBB);
 
+  /// Adds live-out registers from basic block \p MBB, taking associated
+  /// lane masks into consideration.
+  void addBlockLiveOuts(const MachineBasicBlock &MBB);
+
   /// Adds pristine registers. Pristine registers are callee saved registers
   /// that are unused in the function.
   void addPristines(const MachineFunction &MF);
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
index bc711382420be..f1d31daaea530 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -151,23 +151,34 @@ bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
   return true;
 }
 
+/// Adds a register, taking associated lane masks into consideration.
+void LivePhysRegs::addRegMaskPair(
+    const MachineBasicBlock::RegisterMaskPair &Pair) {
+  MCRegister Reg = Pair.PhysReg;
+  LaneBitmask Mask = Pair.LaneMask;
+  MCSubRegIndexIterator S(Reg, TRI);
+  assert(Mask.any() && "Invalid livein mask");
+  if (Mask.all() || !S.isValid()) {
+    addReg(Reg);
+    return;
+  }
+  for (; S.isValid(); ++S) {
+    unsigned SI = S.getSubRegIndex();
+    if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
+      addReg(S.getSubReg());
+  }
+}
+
 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
 void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
-  for (const auto &LI : MBB.liveins()) {
-    MCRegister Reg = LI.PhysReg;
-    LaneBitmask Mask = LI.LaneMask;
-    MCSubRegIndexIterator S(Reg, TRI);
-    assert(Mask.any() && "Invalid livein mask");
-    if (Mask.all() || !S.isValid()) {
-      addReg(Reg);
-      continue;
-    }
-    for (; S.isValid(); ++S) {
-      unsigned SI = S.getSubRegIndex();
-      if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
-        addReg(S.getSubReg());
-    }
-  }
+  for (const auto &LI : MBB.liveins())
+    addRegMaskPair(LI);
+}
+
+/// Add live-out registers of basic block \p MBB to \p LiveRegs.
+void LivePhysRegs::addBlockLiveOuts(const MachineBasicBlock &MBB) {
+  for (const auto &LO : MBB.liveouts())
+    addRegMaskPair(LO);
 }
 
 /// Adds all callee saved registers to \p LiveRegs.
@@ -207,9 +218,7 @@ void LivePhysRegs::addPristines(const MachineFunction &MF) {
 }
 
 void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
-  // To get the live-outs we simply merge the live-ins of all successors.
-  for (const MachineBasicBlock *Succ : MBB.successors())
-    addBlockLiveIns(*Succ);
+  addBlockLiveOuts(MBB);
   if (MBB.isReturnBlock()) {
     // Return blocks are a special case because we currently don't mark up
     // return instructions completely: specifically, there is no explicit
@@ -356,8 +365,8 @@ bool llvm::isPhysRegUsedAfter(Register Reg, MachineBasicBlock::iterator MBI) {
 
   // If we hit the end of the block, check whether Reg is live into a
   //  successor.
-  for (MachineBasicBlock *Succ : MBB->successors())
-    if (Succ->isLiveIn(Reg))
+  for (const auto &LO : MBB->liveouts())
+    if (LO.PhysReg == MCRegister(Reg) && LO.LaneMask.any())
       return true;
 
   return false;
diff --git a/llvm/lib/CodeGen/LiveRegUnits.cpp b/llvm/lib/CodeGen/LiveRegUnits.cpp
index d9c56b87a6bf4..0d87062169585 100644
--- a/llvm/lib/CodeGen/LiveRegUnits.cpp
+++ b/llvm/lib/CodeGen/LiveRegUnits.cpp
@@ -94,8 +94,8 @@ static void addBlockLiveIns(LiveRegUnits &LiveUnits,
 /// Add live-out registers of basic block \p MBB to \p LiveUnits.
 static void addBlockLiveOuts(LiveRegUnits &LiveUnits,
                              const MachineBasicBlock &MBB) {
-  for (const auto &LI : MBB.liveouts())
-    LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
+  for (const auto &LO : MBB.liveouts())
+    LiveUnits.addRegMasked(LO.PhysReg, LO.LaneMask);
 }
 
 /// Adds all callee saved registers to \p LiveUnits.

``````````

</details>


https://github.com/llvm/llvm-project/pull/154728