[llvm] [AArch64] Move BSL generation to lowering. (PR #151855)

[David Green via llvm-commits]

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@@ -14808,14 +14800,13 @@ static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   // We only have to look for constant vectors here since the general, variable
   // case can be handled in TableGen.
   unsigned Bits = VT.getScalarSizeInBits();
-  uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
   for (int i = 1; i >= 0; --i)
     for (int j = 1; j >= 0; --j) {
       APInt Val1, Val2;
 
       if (ISD::isConstantSplatVector(N0->getOperand(i).getNode(), Val1) &&
           ISD::isConstantSplatVector(N1->getOperand(j).getNode(), Val2) &&
-          (BitMask & ~Val1.getZExtValue()) == Val2.getZExtValue()) {
+          ~Val1.trunc(Bits) == Val2.trunc(Bits)) {
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davemgreen wrote:

Yeah - I'm not sure this one is necessary, but the one below helps with buildvectors that post type legalization will look like `v8i16 BUILD_VECTOR i32 a, i32 b, etc`. We often need to truncate the constants to be the size of the final vector. CN0 might be -1 for example.

https://github.com/llvm/llvm-project/pull/151855