[llvm] [RISCV] Move volatile check to isCandidate in VL optimizer. NFC (PR #154685)

[Luke Lau via llvm-commits]

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/154685

This keeps it closer to the other legality checks like the FP exceptions check.
It also means that isSupportedInstr only needs to check the opcode, which allows it to be replaced with a TSFlags based check in a later patch.


>From e3b05dd8b8dba427c81da7307e8c3d4ab5b1628a Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Thu, 21 Aug 2025 15:11:36 +0800
Subject: [PATCH] [RISCV] Move volatile check to isCandidate in VL optimizer.
 NFC

This keeps it closer to the other legality checks like the FP exceptions check.
It also means that isSupportedInstr only needs to check the opcode, which allows it to be replaced with a TSFlags based check in a later patch.
---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index f973e75840dc0..53557049ea33c 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -847,13 +847,7 @@ static bool isSupportedInstr(const MachineInstr &MI) {
   case RISCV::VLUXEI32_V:
   case RISCV::VLOXEI32_V:
   case RISCV::VLUXEI64_V:
-  case RISCV::VLOXEI64_V: {
-    for (const MachineMemOperand *MMO : MI.memoperands())
-      if (MMO->isVolatile())
-        return false;
-    return true;
-  }
-
+  case RISCV::VLOXEI64_V:
   // Vector Single-Width Integer Add and Subtract
   case RISCV::VADD_VI:
   case RISCV::VADD_VV:
@@ -1292,6 +1286,13 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
     return false;
   }
 
+  for (const MachineMemOperand *MMO : MI.memoperands()) {
+    if (MMO->isVolatile()) {
+      LLVM_DEBUG(dbgs() << "Not a candidate because contains volatile MMO\n");
+      return false;
+    }
+  }
+
   // Some instructions that produce vectors have semantics that make it more
   // difficult to determine whether the VL can be reduced. For example, some
   // instructions, such as reductions, may write lanes past VL to a scalar