[llvm] [RISC-V] Add P-ext MC Support for More Pair Operations (PR #154088)

[Qihan Cai via llvm-commits]

https://github.com/realqhc updated https://github.com/llvm/llvm-project/pull/154088

>From e243f9a9fef77a836e635f83be115a1128fda6c5 Mon Sep 17 00:00:00 2001
From: Qihan Cai <caiqihan021 at hotmail.com>
Date: Mon, 18 Aug 2025 20:34:20 +1000
Subject: [PATCH 1/2] [RISC-V] Add P-ext MC Support for More Pair Operations

This patch implements pages 18-20 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

Documentation:
jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf
jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf
---
 llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 52 ++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 157bad8034072..5f583eff2d763 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -149,6 +149,48 @@ class RVPShiftB_ri<bits<3> f, bits<3> funct3, string opcodestr>
   let Inst{22-20} = shamt;
 }
 
+class RVPPairShift_ri<bits<3> f, string opcodestr, Operand ImmType>
+    : RVInst<(outs GPRPairRV32:$rd), (ins GPR:$rs1, ImmType:$shamt), opcodestr,
+                  "$rd, $rs1, $shamt"> {
+  bits<5> rd;
+
+  let Inst{31}    = 0b0;
+  let Inst{30-28} = f;
+  let Inst{27}    = 0b0;
+  let Inst{14-12} = 0b010;
+  let Inst{11-8}  = rd{4-1};
+  let Inst{7}     = 0b0;
+  let Inst{6-0}   = OPC_OP_IMM_32.Value;
+
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+}
+
+class RVPPairShiftW_ri<bits<3> f, string opcodestr>
+    : RVPPairShift_ri<f, opcodestr, uimm6> {
+  bits<6> shamt;
+
+  let Inst{26} = 0b1;
+  let Inst{25-20} = shamt;
+}
+
+class RVPPairShiftH_ri<bits<3> f, string opcodestr>
+    : RVPPairShift_ri<f, opcodestr, uimm5> {
+  bits<5> shamt;
+
+  let Inst{26-25} = 0b01;
+  let Inst{24-20} = shamt;
+}
+
+class RVPPairShiftB_ri<bits<3> f, string opcodestr>
+    : RVPPairShift_ri<f, opcodestr, uimm4> {
+  bits<4> shamt;
+
+  let Inst{26-24} = 0b001;
+  let Inst{23-20} = shamt;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVPUnary_ri<bits<2> w, bits<5> uf, string opcodestr>
     : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
@@ -578,3 +620,13 @@ let Predicates = [HasStdExtP, IsRV64] in {
   def PPACKT_W    : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;
   def PACKT_RV64  : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;
 } // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP, IsRV32] in {
+  def PWSLLI_B : RVPPairShiftB_ri<0b000, "pwslli.b">;
+  def PWSLLI_H : RVPPairShiftH_ri<0b000, "pwslli.h">;
+  def WSLLI    : RVPPairShiftW_ri<0b000, "wslli">;
+
+  def PWSLAI_B : RVPPairShiftB_ri<0b100, "pwslai.b">;
+  def PWSLAI_H : RVPPairShiftH_ri<0b100, "pwslai.h">;
+  def WSLAI    : RVPPairShiftW_ri<0b100, "wslai">;
+} // Predicates = [HasStdExtP, IsRV32]

>From 0523aa2cf4c23a0eeeb0599a4dfca80af2095ee9 Mon Sep 17 00:00:00 2001
From: Qihan Cai <caiqihan021 at hotmail.com>
Date: Thu, 21 Aug 2025 15:40:34 +1000
Subject: [PATCH 2/2] add missing rs1, rename RVPPairShift to RVPWideningShift

---
 llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 28 +++++++++++++-----------
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 5f583eff2d763..066c9fbf5e2fb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -149,14 +149,16 @@ class RVPShiftB_ri<bits<3> f, bits<3> funct3, string opcodestr>
   let Inst{22-20} = shamt;
 }
 
-class RVPPairShift_ri<bits<3> f, string opcodestr, Operand ImmType>
+class RVPWideningShift_ri<bits<3> f, string opcodestr, Operand ImmType>
     : RVInst<(outs GPRPairRV32:$rd), (ins GPR:$rs1, ImmType:$shamt), opcodestr,
                   "$rd, $rs1, $shamt"> {
+  bits<5> rs1;
   bits<5> rd;
 
   let Inst{31}    = 0b0;
   let Inst{30-28} = f;
   let Inst{27}    = 0b0;
+  let Inst{19-15} = rs1;
   let Inst{14-12} = 0b010;
   let Inst{11-8}  = rd{4-1};
   let Inst{7}     = 0b0;
@@ -167,24 +169,24 @@ class RVPPairShift_ri<bits<3> f, string opcodestr, Operand ImmType>
   let mayStore = 0;
 }
 
-class RVPPairShiftW_ri<bits<3> f, string opcodestr>
-    : RVPPairShift_ri<f, opcodestr, uimm6> {
+class RVPWideningShiftW_ri<bits<3> f, string opcodestr>
+    : RVPWideningShift_ri<f, opcodestr, uimm6> {
   bits<6> shamt;
 
   let Inst{26} = 0b1;
   let Inst{25-20} = shamt;
 }
 
-class RVPPairShiftH_ri<bits<3> f, string opcodestr>
-    : RVPPairShift_ri<f, opcodestr, uimm5> {
+class RVPWideningShiftH_ri<bits<3> f, string opcodestr>
+    : RVPWideningShift_ri<f, opcodestr, uimm5> {
   bits<5> shamt;
 
   let Inst{26-25} = 0b01;
   let Inst{24-20} = shamt;
 }
 
-class RVPPairShiftB_ri<bits<3> f, string opcodestr>
-    : RVPPairShift_ri<f, opcodestr, uimm4> {
+class RVPWideningShiftB_ri<bits<3> f, string opcodestr>
+    : RVPWideningShift_ri<f, opcodestr, uimm4> {
   bits<4> shamt;
 
   let Inst{26-24} = 0b001;
@@ -622,11 +624,11 @@ let Predicates = [HasStdExtP, IsRV64] in {
 } // Predicates = [HasStdExtP, IsRV64]
 
 let Predicates = [HasStdExtP, IsRV32] in {
-  def PWSLLI_B : RVPPairShiftB_ri<0b000, "pwslli.b">;
-  def PWSLLI_H : RVPPairShiftH_ri<0b000, "pwslli.h">;
-  def WSLLI    : RVPPairShiftW_ri<0b000, "wslli">;
+  def PWSLLI_B : RVPWideningShiftB_ri<0b000, "pwslli.b">;
+  def PWSLLI_H : RVPWideningShiftH_ri<0b000, "pwslli.h">;
+  def WSLLI    : RVPWideningShiftW_ri<0b000, "wslli">;
 
-  def PWSLAI_B : RVPPairShiftB_ri<0b100, "pwslai.b">;
-  def PWSLAI_H : RVPPairShiftH_ri<0b100, "pwslai.h">;
-  def WSLAI    : RVPPairShiftW_ri<0b100, "wslai">;
+  def PWSLAI_B : RVPWideningShiftB_ri<0b100, "pwslai.b">;
+  def PWSLAI_H : RVPWideningShiftH_ri<0b100, "pwslai.h">;
+  def WSLAI    : RVPWideningShiftW_ri<0b100, "wslai">;
 } // Predicates = [HasStdExtP, IsRV32]