[llvm] [SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 1) (PR #143102)

[Björn Pettersson via llvm-commits]

bjope wrote:

Ping!

Would be really nice to move forward with this patch somehow, to finally get back to fixing the miscompiles we saw in https://github.com/llvm/llvm-project/issues/138513 (which is where I started off 3-4 months ago).

I don't know if the remaining diffs are acceptable now?

The aarch/sve and riscv/rvv diffs can be resolved by using ISD::POISON instead of ISD::UNDEF in convertToScalableVector. We could perhaps do that as a follow-up (to get a motivating test case...).

The diff here https://github.com/llvm/llvm-project/pull/143102/files#diff-3f4fe0b0594906b6df9b5eef955cf7fbc242076e17787dbc845f2adc40ee8d8f is perhaps a bit unfortunate. But I don't have a good solution. However, the IR is not expected to look like that when entering llc, since instcombine would get rid of the insertelement instructions that insert undef. I think the situation was similar for the X86 (SpinningCube) test case that show a diff.



https://github.com/llvm/llvm-project/pull/143102