[llvm] [AArch64] Improve lowering for scalable masked deinterleaving loads (PR #154338)

[Cullen Rhodes via llvm-commits]

================
@@ -27010,6 +27011,121 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return NVCAST;
 }
 
+static SDValue performVectorDeinterleaveCombine(
+    SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) {
+  unsigned NumParts = N->getNumOperands();
+  if (NumParts != 2 && NumParts != 4)
----------------
c-rhodes wrote:

missed a test

https://github.com/llvm/llvm-project/pull/154338