[llvm] [llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (PR #142529)

Lakshay Kumar via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 20 06:00:45 PDT 2025


================
@@ -8891,6 +8893,7 @@ class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
   bits<1> shift;
   let Inst{15-13} = cmode{3-1};
   let Inst{12}    = shift;
+  let Inst{30} = Q;
----------------
lakshayk-nv wrote:

Sure, This change was in anticipation to somehow use the `Q bit` (30th bit of instruction's encoding). But, Now it is irrelevant.

https://github.com/llvm/llvm-project/pull/142529


More information about the llvm-commits mailing list