[llvm] 0fa6fdf - AMDGPU: Correct inst size for av_mov_b32_imm_pseudo (#154459)

[via llvm-commits]

Author: Matt Arsenault
Date: 2025-08-20T17:01:48+09:00
New Revision: 0fa6fdfbb8652c0311d27333934cc4e102df1df2

URL: https://github.com/llvm/llvm-project/commit/0fa6fdfbb8652c0311d27333934cc4e102df1df2
DIFF: https://github.com/llvm/llvm-project/commit/0fa6fdfbb8652c0311d27333934cc4e102df1df2.diff

LOG: AMDGPU: Correct inst size for av_mov_b32_imm_pseudo (#154459)

In the AGPR case this will be an 8 byte instruction,
which is part of why this case is a pain to deal with in the
first place.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index bd5dfa92a8e43..d3c15bd8f672a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -155,7 +155,8 @@ def AV_MOV_B32_IMM_PSEUDO
   let VOP3 = 1;
   let isMoveImm = 1;
   let SchedRW = [Write32Bit];
-  let Size = 4;
+  let Size = 8;
+  let FixedSize = true;
   let UseNamedOperandTable = 1;
 }