[llvm] [AMDGPU] Extending wave reduction intrinsics for `i64` types - 1 (PR #150169)

[Matt Arsenault via llvm-commits]

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@@ -5128,16 +5132,22 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
   bool isSGPR = TRI->isSGPRClass(MRI.getRegClass(SrcReg));
   Register DstReg = MI.getOperand(0).getReg();
   MachineBasicBlock *RetBB = nullptr;
+  bool is32BitOpc = TRI->getRegSizeInBits(*MRI.getRegClass(DstReg)) == 32;
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arsenm wrote:

In general I think it works out uglier. But the size of the value doesn't always match the size of the register class. Plus it's easier to miss applying a subregister to the raw class 

https://github.com/llvm/llvm-project/pull/150169