[llvm] 5868580 - [GlobalISel][AArch64] Add saturated truncate tests. NFC (#154329)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 19 08:11:15 PDT 2025
Author: jyli0116
Date: 2025-08-19T16:11:11+01:00
New Revision: 586858015e57c0508e233e39a91dceb1fcc78934
URL: https://github.com/llvm/llvm-project/commit/586858015e57c0508e233e39a91dceb1fcc78934
DIFF: https://github.com/llvm/llvm-project/commit/586858015e57c0508e233e39a91dceb1fcc78934.diff
LOG: [GlobalISel][AArch64] Add saturated truncate tests. NFC (#154329)
Added GlobalISel tests for saturated truncate.
Added:
Modified:
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
llvm/test/CodeGen/AArch64/qmovn.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index 83ea72c865283..d205b133fbe8c 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -1,15 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel=0| FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-GI
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI
; i32 saturate
define <2 x i32> @stest_f64i32(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f64i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f64i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f64i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI0_1
+; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI0_0
+; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
+; CHECK-CVT-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f64i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI0_1
+; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI0_0
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>
@@ -21,15 +57,43 @@ entry:
}
define <2 x i32> @utest_f64i32(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fcvtzu w9, d1
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w9
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f64i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: mov d1, v0.d[1]
+; CHECK-CVT-SD-NEXT: fcvtzu w8, d0
+; CHECK-CVT-SD-NEXT: fcvtzu w9, d1
+; CHECK-CVT-SD-NEXT: fmov s0, w8
+; CHECK-CVT-SD-NEXT: mov v0.s[1], w9
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f64i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-SD-NEXT: fcvtzu w8, d0
+; CHECK-FP16-SD-NEXT: fcvtzu w9, d1
+; CHECK-FP16-SD-NEXT: fmov s0, w8
+; CHECK-FP16-SD-NEXT: mov v0.s[1], w9
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f64i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f64i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i64>
%0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>
@@ -39,11 +103,39 @@ entry:
}
define <2 x i32> @ustest_f64i32(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f64i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f64i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f64i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f64i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: cmgt v1.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>
@@ -55,10 +147,57 @@ entry:
}
define <4 x i32> @stest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: stest_f32i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f32i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f32i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f32i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI3_1
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI3_0
+; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f32i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI3_1
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI3_0
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
@@ -70,10 +209,43 @@ entry:
}
define <4 x i32> @utest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: utest_f32i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f32i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f32i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f32i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f32i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i64>
%0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -83,10 +255,51 @@ entry:
}
define <4 x i32> @ustest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: ustest_f32i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f32i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f32i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f32i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f32i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -98,11 +311,68 @@ entry:
}
define <4 x i32> @stest_f16i32(<4 x half> %x) {
-; CHECK-LABEL: stest_f16i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI6_1
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI6_0
+; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_1
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
@@ -114,11 +384,54 @@ entry:
}
define <4 x i32> @utesth_f16i32(<4 x half> %x) {
-; CHECK-LABEL: utesth_f16i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
%0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -128,11 +441,62 @@ entry:
}
define <4 x i32> @ustest_f16i32(<4 x half> %x) {
-; CHECK-LABEL: ustest_f16i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i32:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f16i32:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -146,15 +510,45 @@ entry:
; i16 saturate
define <2 x i16> @stest_f64i16(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: movi v1.2s, #127, msl #8
-; CHECK-NEXT: xtn v0.2s, v0.2d
-; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: mvni v1.2s, #127, msl #8
-; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f64i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: movi v1.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f64i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: movi v1.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f64i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: movi v1.2s, #127, msl #8
+; CHECK-CVT-GI-NEXT: mvni v2.2s, #127, msl #8
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-CVT-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f64i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: movi v1.2s, #127, msl #8
+; CHECK-FP16-GI-NEXT: mvni v2.2s, #127, msl #8
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-FP16-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
%0 = icmp slt <2 x i32> %conv, <i32 32767, i32 32767>
@@ -202,11 +596,37 @@ entry:
}
define <4 x i16> @stest_f32i16(<4 x float> %x) {
-; CHECK-LABEL: stest_f32i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f32i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f32i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f32i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f32i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%0 = icmp slt <4 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767>
@@ -218,11 +638,33 @@ entry:
}
define <4 x i16> @utest_f32i16(<4 x float> %x) {
-; CHECK-LABEL: utest_f32i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f32i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f32i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f32i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f32i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i32>
%0 = icmp ult <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -232,11 +674,37 @@ entry:
}
define <4 x i16> @ustest_f32i16(<4 x float> %x) {
-; CHECK-LABEL: ustest_f32i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f32i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f32i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f32i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v2.4s
+; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f32i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v2.4s
+; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%0 = icmp slt <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -248,20 +716,50 @@ entry:
}
define <8 x i16> @stest_f16i16(<8 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i16:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: stest_f16i16:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: smax v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: smax v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
@@ -273,20 +771,44 @@ entry:
}
define <8 x i16> @utesth_f16i16(<8 x half> %x) {
-; CHECK-CVT-LABEL: utesth_f16i16:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
-; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: utesth_f16i16:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: fcvtzu v2.4s, v2.4s
+; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: umin v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: umin v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <8 x half> %x to <8 x i32>
%0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
@@ -296,20 +818,50 @@ entry:
}
define <8 x i16> @ustest_f16i16(<8 x half> %x) {
-; CHECK-CVT-LABEL: ustest_f16i16:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: ustest_f16i16:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f16i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: movi v3.2d, #0000000000000000
+; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smax v1.4s, v2.4s, v3.4s
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v3.4s
+; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: movi v3.2d, #0000000000000000
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smax v1.4s, v2.4s, v3.4s
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v3.4s
+; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
@@ -323,10 +875,139 @@ entry:
; i64 saturate
define <2 x i64> @stest_f64i64(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f64i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f64i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f64i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
+; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
+; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: fmov d0, d8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: cmp x19, x21
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: cmp x20, #0
+; CHECK-CVT-GI-NEXT: cset w9, mi
+; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-CVT-GI-NEXT: cmp x0, x21
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: cmp x1, #0
+; CHECK-CVT-GI-NEXT: cset w10, mi
+; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x9, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f64i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
+; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
+; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: fmov d0, d8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: cmp x19, x21
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: cmp x20, #0
+; CHECK-FP16-GI-NEXT: cset w9, mi
+; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-FP16-GI-NEXT: cmp x0, x21
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: cmp x1, #0
+; CHECK-FP16-GI-NEXT: cset w10, mi
+; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x9, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
@@ -338,34 +1019,131 @@ entry:
}
define <2 x i64> @utest_f64i64(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f64i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
+; CHECK-CVT-SD-NEXT: bl __fixunsdfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixunsdfti
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f64i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
+; CHECK-FP16-SD-NEXT: bl __fixunsdfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixunsdfti
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f64i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixunsdfti
+; CHECK-CVT-GI-NEXT: fmov d0, d8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixunsdfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f64i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixunsdfti
+; CHECK-FP16-GI-NEXT: fmov d0, d8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixunsdfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -375,42 +1153,179 @@ entry:
}
define <2 x i64> @ustest_f64i64(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csel x10, x19, xzr, lt
-; CHECK-NEXT: csinc x11, x20, xzr, lt
-; CHECK-NEXT: cmp xzr, x10
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ngcs xzr, x11
-; CHECK-NEXT: csel x10, x10, xzr, lt
-; CHECK-NEXT: cmp xzr, x8
-; CHECK-NEXT: ngcs xzr, x9
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: csel x8, x8, xzr, lt
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f64i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixdfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
+; CHECK-CVT-SD-NEXT: bl __fixdfti
+; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #1
+; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp xzr, x10
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: ngcs xzr, x11
+; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp xzr, x8
+; CHECK-CVT-SD-NEXT: ngcs xzr, x9
+; CHECK-CVT-SD-NEXT: fmov d0, x10
+; CHECK-CVT-SD-NEXT: csel x8, x8, xzr, lt
+; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f64i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixdfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
+; CHECK-FP16-SD-NEXT: bl __fixdfti
+; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #1
+; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp xzr, x10
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: ngcs xzr, x11
+; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp xzr, x8
+; CHECK-FP16-SD-NEXT: ngcs xzr, x9
+; CHECK-FP16-SD-NEXT: fmov d0, x10
+; CHECK-FP16-SD-NEXT: csel x8, x8, xzr, lt
+; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f64i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: fmov d0, d8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lt
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lt
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f64i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: fmov d0, d8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lt
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lt
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -422,11 +1337,143 @@ entry:
}
define <2 x i64> @stest_f32i64(<2 x float> %x) {
-; CHECK-LABEL: stest_f32i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f32i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f32i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f32i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
+; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: fmov s0, s8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: cmp x19, x21
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: cmp x20, #0
+; CHECK-CVT-GI-NEXT: cset w9, mi
+; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-CVT-GI-NEXT: cmp x0, x21
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: cmp x1, #0
+; CHECK-CVT-GI-NEXT: cset w10, mi
+; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x9, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f32i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
+; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: fmov s0, s8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: cmp x19, x21
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: cmp x20, #0
+; CHECK-FP16-GI-NEXT: cset w9, mi
+; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-FP16-GI-NEXT: cmp x0, x21
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: cmp x1, #0
+; CHECK-FP16-GI-NEXT: cset w10, mi
+; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x9, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
@@ -438,35 +1485,135 @@ entry:
}
define <2 x i64> @utest_f32i64(<2 x float> %x) {
-; CHECK-LABEL: utest_f32i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f32i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
+; CHECK-CVT-SD-NEXT: bl __fixunssfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixunssfti
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f32i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
+; CHECK-FP16-SD-NEXT: bl __fixunssfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixunssfti
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f32i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
+; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixunssfti
+; CHECK-CVT-GI-NEXT: fmov s0, s8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixunssfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f32i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
+; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixunssfti
+; CHECK-FP16-GI-NEXT: fmov s0, s8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixunssfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x float> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -476,43 +1623,183 @@ entry:
}
define <2 x i64> @ustest_f32i64(<2 x float> %x) {
-; CHECK-LABEL: ustest_f32i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csinc x8, x1, xzr, lt
-; CHECK-NEXT: csel x9, x0, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csel x10, x19, xzr, lt
-; CHECK-NEXT: csinc x11, x20, xzr, lt
-; CHECK-NEXT: cmp xzr, x10
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ngcs xzr, x11
-; CHECK-NEXT: csel x10, x10, xzr, lt
-; CHECK-NEXT: cmp xzr, x9
-; CHECK-NEXT: ngcs xzr, x8
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: csel x8, x9, xzr, lt
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f32i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixsfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
+; CHECK-CVT-SD-NEXT: bl __fixsfti
+; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csinc x8, x1, xzr, lt
+; CHECK-CVT-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #1
+; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp xzr, x10
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: ngcs xzr, x11
+; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp xzr, x9
+; CHECK-CVT-SD-NEXT: ngcs xzr, x8
+; CHECK-CVT-SD-NEXT: fmov d0, x10
+; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f32i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixsfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
+; CHECK-FP16-SD-NEXT: bl __fixsfti
+; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csinc x8, x1, xzr, lt
+; CHECK-FP16-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #1
+; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp xzr, x10
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: ngcs xzr, x11
+; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp xzr, x9
+; CHECK-FP16-SD-NEXT: ngcs xzr, x8
+; CHECK-FP16-SD-NEXT: fmov d0, x10
+; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f32i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
+; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: fmov s0, s8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lt
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lt
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f32i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
+; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: fmov s0, s8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lt
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lt
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -524,27 +1811,121 @@ entry:
}
define <2 x i64> @stest_f16i64(<2 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i64:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fcvt s1, h1
-; CHECK-CVT-NEXT: fcvtzs x8, s0
-; CHECK-CVT-NEXT: fcvtzs x9, s1
-; CHECK-CVT-NEXT: fmov d0, x8
-; CHECK-CVT-NEXT: mov v0.d[1], x9
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: stest_f16i64:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-NEXT: fcvtzs x8, h0
-; CHECK-FP16-NEXT: fcvtzs x9, h1
-; CHECK-FP16-NEXT: fmov d0, x8
-; CHECK-FP16-NEXT: mov v0.d[1], x9
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-SD-NEXT: fcvt s0, h0
+; CHECK-CVT-SD-NEXT: fcvt s1, h1
+; CHECK-CVT-SD-NEXT: fcvtzs x8, s0
+; CHECK-CVT-SD-NEXT: fcvtzs x9, s1
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], x9
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-SD-NEXT: fcvtzs x8, h0
+; CHECK-FP16-SD-NEXT: fcvtzs x9, h1
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], x9
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x10, s1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cmp x9, x8
+; CHECK-CVT-GI-NEXT: cset w12, lo
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: asr x13, x10, #63
+; CHECK-CVT-GI-NEXT: cset w14, mi
+; CHECK-CVT-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-CVT-GI-NEXT: cmp x10, x8
+; CHECK-CVT-GI-NEXT: cset w14, lo
+; CHECK-CVT-GI-NEXT: cmp x13, #0
+; CHECK-CVT-GI-NEXT: cset w15, mi
+; CHECK-CVT-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-CVT-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w14, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-CVT-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x9, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x8, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x9
+; CHECK-CVT-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x8
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h0
+; CHECK-FP16-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: fcvtzs x10, h1
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: cmp x9, x8
+; CHECK-FP16-GI-NEXT: cset w12, lo
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w14, mi
+; CHECK-FP16-GI-NEXT: asr x13, x10, #63
+; CHECK-FP16-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-FP16-GI-NEXT: cmp x10, x8
+; CHECK-FP16-GI-NEXT: cset w14, lo
+; CHECK-FP16-GI-NEXT: cmp x13, #0
+; CHECK-FP16-GI-NEXT: cset w15, mi
+; CHECK-FP16-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-FP16-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w14, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-FP16-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x9, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x8, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x9
+; CHECK-FP16-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x8
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
@@ -556,35 +1937,87 @@ entry:
}
define <2 x i64> @utesth_f16i64(<2 x half> %x) {
-; CHECK-LABEL: utesth_f16i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
+; CHECK-CVT-SD-NEXT: bl __fixunshfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixunshfti
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
+; CHECK-FP16-SD-NEXT: bl __fixunshfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixunshfti
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzu x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzu x9, s1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzu x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzu x9, h1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x half> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -594,43 +2027,159 @@ entry:
}
define <2 x i64> @ustest_f16i64(<2 x half> %x) {
-; CHECK-LABEL: ustest_f16i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csinc x8, x1, xzr, lt
-; CHECK-NEXT: csel x9, x0, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csel x10, x19, xzr, lt
-; CHECK-NEXT: csinc x11, x20, xzr, lt
-; CHECK-NEXT: cmp xzr, x10
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ngcs xzr, x11
-; CHECK-NEXT: csel x10, x10, xzr, lt
-; CHECK-NEXT: cmp xzr, x9
-; CHECK-NEXT: ngcs xzr, x8
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: csel x8, x9, xzr, lt
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixhfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
+; CHECK-CVT-SD-NEXT: bl __fixhfti
+; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csinc x8, x1, xzr, lt
+; CHECK-CVT-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #1
+; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp xzr, x10
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: ngcs xzr, x11
+; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp xzr, x9
+; CHECK-CVT-SD-NEXT: ngcs xzr, x8
+; CHECK-CVT-SD-NEXT: fmov d0, x10
+; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f16i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixhfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
+; CHECK-FP16-SD-NEXT: bl __fixhfti
+; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csinc x8, x1, xzr, lt
+; CHECK-FP16-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #1
+; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp xzr, x10
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: ngcs xzr, x11
+; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp xzr, x9
+; CHECK-FP16-SD-NEXT: ngcs xzr, x8
+; CHECK-FP16-SD-NEXT: fmov d0, x10
+; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s1
+; CHECK-CVT-GI-NEXT: asr x10, x8, #63
+; CHECK-CVT-GI-NEXT: cmp x10, #1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cset w12, lt
+; CHECK-CVT-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-CVT-GI-NEXT: cmp x11, #1
+; CHECK-CVT-GI-NEXT: cset w13, lt
+; CHECK-CVT-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w13, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h1
+; CHECK-FP16-GI-NEXT: asr x10, x8, #63
+; CHECK-FP16-GI-NEXT: cmp x10, #1
+; CHECK-FP16-GI-NEXT: cset w12, lt
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-FP16-GI-NEXT: cmp x11, #1
+; CHECK-FP16-GI-NEXT: cset w13, lt
+; CHECK-FP16-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w13, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -646,11 +2195,45 @@ entry:
; i32 saturate
define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f64i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f64i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f64i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI27_1
+; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI27_0
+; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_0]
+; CHECK-CVT-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f64i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI27_1
+; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI27_0
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI27_0]
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)
@@ -660,15 +2243,43 @@ entry:
}
define <2 x i32> @utest_f64i32_mm(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fcvtzu w9, d1
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w9
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f64i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: mov d1, v0.d[1]
+; CHECK-CVT-SD-NEXT: fcvtzu w8, d0
+; CHECK-CVT-SD-NEXT: fcvtzu w9, d1
+; CHECK-CVT-SD-NEXT: fmov s0, w8
+; CHECK-CVT-SD-NEXT: mov v0.s[1], w9
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f64i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
+; CHECK-FP16-SD-NEXT: fcvtzu w8, d0
+; CHECK-FP16-SD-NEXT: fcvtzu w9, d1
+; CHECK-FP16-SD-NEXT: fmov s0, w8
+; CHECK-FP16-SD-NEXT: mov v0.s[1], w9
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f64i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f64i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -677,11 +2288,39 @@ entry:
}
define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f64i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f64i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f64i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f64i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: cmgt v1.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -691,10 +2330,57 @@ entry:
}
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
-; CHECK-LABEL: stest_f32i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f32i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f32i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f32i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI30_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI30_0]
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f32i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI30_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI30_0]
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
@@ -704,10 +2390,43 @@ entry:
}
define <4 x i32> @utest_f32i32_mm(<4 x float> %x) {
-; CHECK-LABEL: utest_f32i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f32i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f32i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f32i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f32i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -716,10 +2435,51 @@ entry:
}
define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
-; CHECK-LABEL: ustest_f32i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f32i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f32i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f32i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f32i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -729,11 +2489,68 @@ entry:
}
define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
-; CHECK-LABEL: stest_f16i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI33_1
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI33_0
+; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_1
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
@@ -743,11 +2560,54 @@ entry:
}
define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
-; CHECK-LABEL: utesth_f16i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -756,11 +2616,62 @@ entry:
}
define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
-; CHECK-LABEL: ustest_f16i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i32_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f16i32_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -772,15 +2683,45 @@ entry:
; i16 saturate
define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i16_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: movi v1.2s, #127, msl #8
-; CHECK-NEXT: xtn v0.2s, v0.2d
-; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: mvni v1.2s, #127, msl #8
-; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f64i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: movi v1.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f64i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: movi v1.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f64i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: movi v1.2s, #127, msl #8
+; CHECK-CVT-GI-NEXT: mvni v2.2s, #127, msl #8
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-CVT-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f64i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: movi v1.2s, #127, msl #8
+; CHECK-FP16-GI-NEXT: mvni v2.2s, #127, msl #8
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-FP16-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
%spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>)
@@ -823,11 +2764,37 @@ entry:
}
define <4 x i16> @stest_f32i16_mm(<4 x float> %x) {
-; CHECK-LABEL: stest_f32i16_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f32i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f32i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f32i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f32i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
@@ -837,11 +2804,33 @@ entry:
}
define <4 x i16> @utest_f32i16_mm(<4 x float> %x) {
-; CHECK-LABEL: utest_f32i16_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f32i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f32i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f32i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f32i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i32>
%spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -850,11 +2839,37 @@ entry:
}
define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
-; CHECK-LABEL: ustest_f32i16_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f32i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f32i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f32i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v2.4s
+; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f32i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v2.4s
+; CHECK-FP16-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i32>
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -864,20 +2879,50 @@ entry:
}
define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i16_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: stest_f16i16_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-CVT-GI-NEXT: smax v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-FP16-GI-NEXT: smax v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
@@ -887,20 +2932,44 @@ entry:
}
define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-LABEL: utesth_f16i16_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
-; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: utesth_f16i16_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: fcvtzu v2.4s, v2.4s
+; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: umin v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: umin v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -909,20 +2978,50 @@ entry:
}
define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-LABEL: ustest_f16i16_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: ustest_f16i16_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f16i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: movi v3.2d, #0000000000000000
+; CHECK-CVT-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-GI-NEXT: smax v1.4s, v2.4s, v3.4s
+; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v3.4s
+; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: movi v3.2d, #0000000000000000
+; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: smin v2.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: smax v1.4s, v2.4s, v3.4s
+; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v3.4s
+; CHECK-FP16-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -934,10 +3033,139 @@ entry:
; i64 saturate
define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f64i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f64i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f64i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
+; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
+; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: fmov d0, d8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: cmp x19, x21
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: cmp x20, #0
+; CHECK-CVT-GI-NEXT: cset w9, mi
+; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-CVT-GI-NEXT: cmp x0, x21
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: cmp x1, #0
+; CHECK-CVT-GI-NEXT: cset w10, mi
+; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x9, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f64i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
+; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
+; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: fmov d0, d8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: cmp x19, x21
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: cmp x20, #0
+; CHECK-FP16-GI-NEXT: cset w9, mi
+; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-FP16-GI-NEXT: cmp x0, x21
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: cmp x1, #0
+; CHECK-FP16-GI-NEXT: cset w10, mi
+; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x9, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -947,34 +3175,131 @@ entry:
}
define <2 x i64> @utest_f64i64_mm(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f64i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
+; CHECK-CVT-SD-NEXT: bl __fixunsdfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixunsdfti
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f64i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
+; CHECK-FP16-SD-NEXT: bl __fixunsdfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixunsdfti
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f64i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixunsdfti
+; CHECK-CVT-GI-NEXT: fmov d0, d8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixunsdfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f64i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixunsdfti
+; CHECK-FP16-GI-NEXT: fmov d0, d8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixunsdfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -983,40 +3308,175 @@ entry:
}
define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csinc x10, x20, xzr, lt
-; CHECK-NEXT: csel x11, x19, xzr, lt
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: csel x10, xzr, x11, mi
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: csel x8, xzr, x8, mi
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f64i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixdfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
+; CHECK-CVT-SD-NEXT: bl __fixdfti
+; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #1
+; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-CVT-SD-NEXT: cmp x9, #0
+; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
+; CHECK-CVT-SD-NEXT: fmov d0, x10
+; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f64i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixdfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
+; CHECK-FP16-SD-NEXT: bl __fixdfti
+; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #1
+; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-FP16-SD-NEXT: cmp x9, #0
+; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
+; CHECK-FP16-SD-NEXT: fmov d0, x10
+; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f64i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: fmov d0, d8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixdfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lt
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lt
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f64i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: fmov d0, d8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixdfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lt
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lt
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1026,11 +3486,143 @@ entry:
}
define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
-; CHECK-LABEL: stest_f32i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f32i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f32i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f32i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
+; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: fmov s0, s8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: cmp x19, x21
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: cmp x20, #0
+; CHECK-CVT-GI-NEXT: cset w9, mi
+; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-CVT-GI-NEXT: cmp x0, x21
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: cmp x1, #0
+; CHECK-CVT-GI-NEXT: cset w10, mi
+; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x9, x22
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f32i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
+; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: fmov s0, s8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: cmp x19, x21
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: cmp x20, #0
+; CHECK-FP16-GI-NEXT: cset w9, mi
+; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-FP16-GI-NEXT: cmp x0, x21
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: cmp x1, #0
+; CHECK-FP16-GI-NEXT: cset w10, mi
+; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x9, x22
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -1040,35 +3632,135 @@ entry:
}
define <2 x i64> @utest_f32i64_mm(<2 x float> %x) {
-; CHECK-LABEL: utest_f32i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utest_f32i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
+; CHECK-CVT-SD-NEXT: bl __fixunssfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixunssfti
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utest_f32i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
+; CHECK-FP16-SD-NEXT: bl __fixunssfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixunssfti
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utest_f32i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
+; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixunssfti
+; CHECK-CVT-GI-NEXT: fmov s0, s8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixunssfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lo
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lo
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utest_f32i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
+; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixunssfti
+; CHECK-FP16-GI-NEXT: fmov s0, s8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixunssfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lo
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lo
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1077,41 +3769,179 @@ entry:
}
define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
-; CHECK-LABEL: ustest_f32i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csinc x10, x20, xzr, lt
-; CHECK-NEXT: csel x11, x19, xzr, lt
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: csel x10, xzr, x11, mi
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: csel x8, xzr, x8, mi
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f32i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixsfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
+; CHECK-CVT-SD-NEXT: bl __fixsfti
+; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #1
+; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-CVT-SD-NEXT: cmp x9, #0
+; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
+; CHECK-CVT-SD-NEXT: fmov d0, x10
+; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f32i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixsfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
+; CHECK-FP16-SD-NEXT: bl __fixsfti
+; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #1
+; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-FP16-SD-NEXT: cmp x9, #0
+; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
+; CHECK-FP16-SD-NEXT: fmov d0, x10
+; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f32i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
+; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
+; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: fmov s0, s8
+; CHECK-CVT-GI-NEXT: mov x19, x0
+; CHECK-CVT-GI-NEXT: mov x20, x1
+; CHECK-CVT-GI-NEXT: bl __fixsfti
+; CHECK-CVT-GI-NEXT: cmp x20, #1
+; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: cset w8, lt
+; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-CVT-GI-NEXT: cmp x1, #1
+; CHECK-CVT-GI-NEXT: cset w9, lt
+; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-CVT-GI-NEXT: tst w8, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w9, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f32i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
+; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
+; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: fmov s0, s8
+; CHECK-FP16-GI-NEXT: mov x19, x0
+; CHECK-FP16-GI-NEXT: mov x20, x1
+; CHECK-FP16-GI-NEXT: bl __fixsfti
+; CHECK-FP16-GI-NEXT: cmp x20, #1
+; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: cset w8, lt
+; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-GI-NEXT: cmp x1, #1
+; CHECK-FP16-GI-NEXT: cset w9, lt
+; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-FP16-GI-NEXT: tst w8, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w9, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1121,27 +3951,121 @@ entry:
}
define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i64_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fcvt s1, h1
-; CHECK-CVT-NEXT: fcvtzs x8, s0
-; CHECK-CVT-NEXT: fcvtzs x9, s1
-; CHECK-CVT-NEXT: fmov d0, x8
-; CHECK-CVT-NEXT: mov v0.d[1], x9
-; CHECK-CVT-NEXT: ret
-;
-; CHECK-FP16-LABEL: stest_f16i64_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-NEXT: fcvtzs x8, h0
-; CHECK-FP16-NEXT: fcvtzs x9, h1
-; CHECK-FP16-NEXT: fmov d0, x8
-; CHECK-FP16-NEXT: mov v0.d[1], x9
-; CHECK-FP16-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-SD-NEXT: fcvt s0, h0
+; CHECK-CVT-SD-NEXT: fcvt s1, h1
+; CHECK-CVT-SD-NEXT: fcvtzs x8, s0
+; CHECK-CVT-SD-NEXT: fcvtzs x9, s1
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], x9
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-SD-NEXT: fcvtzs x8, h0
+; CHECK-FP16-SD-NEXT: fcvtzs x9, h1
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], x9
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x10, s1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cmp x9, x8
+; CHECK-CVT-GI-NEXT: cset w12, lo
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: asr x13, x10, #63
+; CHECK-CVT-GI-NEXT: cset w14, mi
+; CHECK-CVT-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-CVT-GI-NEXT: cmp x10, x8
+; CHECK-CVT-GI-NEXT: cset w14, lo
+; CHECK-CVT-GI-NEXT: cmp x13, #0
+; CHECK-CVT-GI-NEXT: cset w15, mi
+; CHECK-CVT-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-CVT-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w14, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-CVT-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x9, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x8, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, pl
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x9
+; CHECK-CVT-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x8
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h0
+; CHECK-FP16-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: fcvtzs x10, h1
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: cmp x9, x8
+; CHECK-FP16-GI-NEXT: cset w12, lo
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w14, mi
+; CHECK-FP16-GI-NEXT: asr x13, x10, #63
+; CHECK-FP16-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-FP16-GI-NEXT: cmp x10, x8
+; CHECK-FP16-GI-NEXT: cset w14, lo
+; CHECK-FP16-GI-NEXT: cmp x13, #0
+; CHECK-FP16-GI-NEXT: cset w15, mi
+; CHECK-FP16-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-FP16-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w14, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-FP16-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x9, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x8, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, pl
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x9
+; CHECK-FP16-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x8
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -1151,35 +4075,87 @@ entry:
}
define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
-; CHECK-LABEL: utesth_f16i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
+; CHECK-CVT-SD-NEXT: bl __fixunshfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixunshfti
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
+; CHECK-FP16-SD-NEXT: bl __fixunshfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixunshfti
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzu x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzu x9, s1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzu x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzu x9, h1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1188,41 +4164,155 @@ entry:
}
define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
-; CHECK-LABEL: ustest_f16i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csinc x10, x20, xzr, lt
-; CHECK-NEXT: csel x11, x19, xzr, lt
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: csel x10, xzr, x11, mi
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: csel x8, xzr, x8, mi
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: sub sp, sp, #48
+; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
+; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
+; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-CVT-SD-NEXT: bl __fixhfti
+; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: mov x19, x0
+; CHECK-CVT-SD-NEXT: mov x20, x1
+; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
+; CHECK-CVT-SD-NEXT: bl __fixhfti
+; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #1
+; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-CVT-SD-NEXT: cmp x9, #0
+; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
+; CHECK-CVT-SD-NEXT: fmov d0, x10
+; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f16i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: sub sp, sp, #48
+; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
+; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
+; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-FP16-SD-NEXT: bl __fixhfti
+; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: mov x19, x0
+; CHECK-FP16-SD-NEXT: mov x20, x1
+; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
+; CHECK-FP16-SD-NEXT: bl __fixhfti
+; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #1
+; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-FP16-SD-NEXT: cmp x9, #0
+; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
+; CHECK-FP16-SD-NEXT: fmov d0, x10
+; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s1
+; CHECK-CVT-GI-NEXT: asr x10, x8, #63
+; CHECK-CVT-GI-NEXT: cmp x10, #1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cset w12, lt
+; CHECK-CVT-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-CVT-GI-NEXT: cmp x11, #1
+; CHECK-CVT-GI-NEXT: cset w13, lt
+; CHECK-CVT-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w13, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h1
+; CHECK-FP16-GI-NEXT: asr x10, x8, #63
+; CHECK-FP16-GI-NEXT: cmp x10, #1
+; CHECK-FP16-GI-NEXT: cset w12, lt
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-FP16-GI-NEXT: cmp x11, #1
+; CHECK-FP16-GI-NEXT: cset w13, lt
+; CHECK-FP16-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w13, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1249,3 +4339,6 @@ declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
declare <2 x i128> @llvm.smin.v2i128(<2 x i128>, <2 x i128>)
declare <2 x i128> @llvm.smax.v2i128(<2 x i128>, <2 x i128>)
declare <2 x i128> @llvm.umin.v2i128(<2 x i128>, <2 x i128>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-CVT: {{.*}}
+; CHECK-FP16: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 77dd6c6425207..e580191ecc55e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-CVT
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
-; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-CVT,CHECK-SD-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-FP16,CHECK-SD-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-CVT,CHECK-GI-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-FP16,CHECK-GI-FP16
; CHECK-GI: warning: Instruction selection used fallback path for test_signed_v4f32_v4i50
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_signed_v4f16_v4i50
@@ -1162,31 +1162,18 @@ declare <7 x i32> @llvm.fptosi.sat.v7f16.v7i32 (<7 x half>)
declare <8 x i32> @llvm.fptosi.sat.v8f16.v8i32 (<8 x half>)
define <1 x i32> @test_signed_v1f16_v1i32(<1 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_signed_v1f16_v1i32:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
-; CHECK-SD-CVT-NEXT: fmov s0, w8
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_signed_v1f16_v1i32:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
-; CHECK-SD-FP16-NEXT: fmov s0, w8
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-CVT-LABEL: test_signed_v1f16_v1i32:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvtzs w8, s0
+; CHECK-CVT-NEXT: fmov s0, w8
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_signed_v1f16_v1i32:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: fcvtzs w8, s0
-; CHECK-GI-CVT-NEXT: fmov s0, w8
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v1f16_v1i32:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs w8, h0
-; CHECK-GI-FP16-NEXT: fmov s0, w8
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v1f16_v1i32:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs w8, h0
+; CHECK-FP16-NEXT: fmov s0, w8
+; CHECK-FP16-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f16.v1i32(<1 x half> %f)
ret <1 x i32> %x
}
@@ -2905,16 +2892,16 @@ define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
}
define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_signed_v4f16_v4i8:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-CVT-NEXT: movi v1.4s, #127
-; CHECK-SD-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-SD-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-SD-CVT-NEXT: mvni v1.4s, #127
-; CHECK-SD-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-SD-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_signed_v4f16_v4i8:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-NEXT: movi v1.4s, #127
+; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-NEXT: mvni v1.4s, #127
+; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: ret
;
; CHECK-SD-FP16-LABEL: test_signed_v4f16_v4i8:
; CHECK-SD-FP16: // %bb.0:
@@ -2925,17 +2912,6 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; CHECK-SD-FP16-NEXT: smax v0.4h, v0.4h, v1.4h
; CHECK-SD-FP16-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i8:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #127
-; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: mvni v1.4s, #127
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-CVT-NEXT: ret
-;
; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i8:
; CHECK-GI-FP16: // %bb.0:
; CHECK-GI-FP16-NEXT: movi v1.4h, #127
@@ -2949,45 +2925,25 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
}
define <4 x i13> @test_signed_v4f16_v4i13(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_signed_v4f16_v4i13:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-CVT-NEXT: movi v1.4s, #15, msl #8
-; CHECK-SD-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-SD-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-SD-CVT-NEXT: mvni v1.4s, #15, msl #8
-; CHECK-SD-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-SD-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_signed_v4f16_v4i13:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs v0.4h, v0.4h
-; CHECK-SD-FP16-NEXT: mvni v1.4h, #240, lsl #8
-; CHECK-SD-FP16-NEXT: movi v2.4h, #240, lsl #8
-; CHECK-SD-FP16-NEXT: smin v0.4h, v0.4h, v1.4h
-; CHECK-SD-FP16-NEXT: smax v0.4h, v0.4h, v2.4h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-CVT-LABEL: test_signed_v4f16_v4i13:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-NEXT: movi v1.4s, #15, msl #8
+; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-NEXT: mvni v1.4s, #15, msl #8
+; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i13:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #15, msl #8
-; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: mvni v1.4s, #15, msl #8
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i13:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs v0.4h, v0.4h
-; CHECK-GI-FP16-NEXT: mvni v1.4h, #240, lsl #8
-; CHECK-GI-FP16-NEXT: movi v2.4h, #240, lsl #8
-; CHECK-GI-FP16-NEXT: smin v0.4h, v0.4h, v1.4h
-; CHECK-GI-FP16-NEXT: smax v0.4h, v0.4h, v2.4h
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v4f16_v4i13:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h
+; CHECK-FP16-NEXT: mvni v1.4h, #240, lsl #8
+; CHECK-FP16-NEXT: movi v2.4h, #240, lsl #8
+; CHECK-FP16-NEXT: smin v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT: smax v0.4h, v0.4h, v2.4h
+; CHECK-FP16-NEXT: ret
%x = call <4 x i13> @llvm.fptosi.sat.v4f16.v4i13(<4 x half> %f)
ret <4 x i13> %x
}
@@ -3000,10 +2956,10 @@ define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; CHECK-SD-CVT-NEXT: sqxtn v0.4h, v0.4s
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_signed_v4f16_v4i16:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs v0.4h, v0.4h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v4f16_v4i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i16:
; CHECK-GI-CVT: // %bb.0:
@@ -3015,11 +2971,6 @@ define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i16:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs v0.4h, v0.4h
-; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i16> @llvm.fptosi.sat.v4f16.v4i16(<4 x half> %f)
ret <4 x i16> %x
}
@@ -3049,133 +3000,69 @@ define <4 x i32> @test_signed_v4f16_v4i32_duplicate(<4 x half> %f) {
}
define <4 x i50> @test_signed_v4f16_v4i50(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_signed_v4f16_v4i50:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-SD-CVT-NEXT: fcvt s2, h0
-; CHECK-SD-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-SD-CVT-NEXT: mov h3, v0.h[2]
-; CHECK-SD-CVT-NEXT: mov h0, v0.h[3]
-; CHECK-SD-CVT-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
-; CHECK-SD-CVT-NEXT: fcvt s1, h1
-; CHECK-SD-CVT-NEXT: fcvtzs x9, s2
-; CHECK-SD-CVT-NEXT: fcvt s2, h3
-; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: fcvtzs x10, s1
-; CHECK-SD-CVT-NEXT: cmp x9, x8
-; CHECK-SD-CVT-NEXT: csel x9, x9, x8, lt
-; CHECK-SD-CVT-NEXT: fcvtzs x12, s2
-; CHECK-SD-CVT-NEXT: cmp x9, x11
-; CHECK-SD-CVT-NEXT: csel x0, x9, x11, gt
-; CHECK-SD-CVT-NEXT: cmp x10, x8
-; CHECK-SD-CVT-NEXT: csel x9, x10, x8, lt
-; CHECK-SD-CVT-NEXT: fcvtzs x10, s0
-; CHECK-SD-CVT-NEXT: cmp x9, x11
-; CHECK-SD-CVT-NEXT: csel x1, x9, x11, gt
-; CHECK-SD-CVT-NEXT: cmp x12, x8
-; CHECK-SD-CVT-NEXT: csel x9, x12, x8, lt
-; CHECK-SD-CVT-NEXT: cmp x9, x11
-; CHECK-SD-CVT-NEXT: csel x2, x9, x11, gt
-; CHECK-SD-CVT-NEXT: cmp x10, x8
-; CHECK-SD-CVT-NEXT: csel x8, x10, x8, lt
-; CHECK-SD-CVT-NEXT: cmp x8, x11
-; CHECK-SD-CVT-NEXT: csel x3, x8, x11, gt
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_signed_v4f16_v4i50:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-SD-FP16-NEXT: fcvtzs x9, h0
-; CHECK-SD-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-SD-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-SD-FP16-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
-; CHECK-SD-FP16-NEXT: mov h0, v0.h[3]
-; CHECK-SD-FP16-NEXT: fcvtzs x10, h1
-; CHECK-SD-FP16-NEXT: cmp x9, x8
-; CHECK-SD-FP16-NEXT: csel x9, x9, x8, lt
-; CHECK-SD-FP16-NEXT: fcvtzs x12, h2
-; CHECK-SD-FP16-NEXT: cmp x9, x11
-; CHECK-SD-FP16-NEXT: csel x0, x9, x11, gt
-; CHECK-SD-FP16-NEXT: cmp x10, x8
-; CHECK-SD-FP16-NEXT: csel x9, x10, x8, lt
-; CHECK-SD-FP16-NEXT: fcvtzs x10, h0
-; CHECK-SD-FP16-NEXT: cmp x9, x11
-; CHECK-SD-FP16-NEXT: csel x1, x9, x11, gt
-; CHECK-SD-FP16-NEXT: cmp x12, x8
-; CHECK-SD-FP16-NEXT: csel x9, x12, x8, lt
-; CHECK-SD-FP16-NEXT: cmp x9, x11
-; CHECK-SD-FP16-NEXT: csel x2, x9, x11, gt
-; CHECK-SD-FP16-NEXT: cmp x10, x8
-; CHECK-SD-FP16-NEXT: csel x8, x10, x8, lt
-; CHECK-SD-FP16-NEXT: cmp x8, x11
-; CHECK-SD-FP16-NEXT: csel x3, x8, x11, gt
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i50:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: fcvt s2, h0
-; CHECK-GI-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov h0, v0.h[3]
-; CHECK-GI-CVT-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvtzs x9, s2
-; CHECK-GI-CVT-NEXT: fcvt s2, h3
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: fcvtzs x10, s1
-; CHECK-GI-CVT-NEXT: cmp x9, x8
-; CHECK-GI-CVT-NEXT: csel x9, x9, x8, lt
-; CHECK-GI-CVT-NEXT: fcvtzs x12, s2
-; CHECK-GI-CVT-NEXT: cmp x9, x11
-; CHECK-GI-CVT-NEXT: csel x0, x9, x11, gt
-; CHECK-GI-CVT-NEXT: cmp x10, x8
-; CHECK-GI-CVT-NEXT: csel x9, x10, x8, lt
-; CHECK-GI-CVT-NEXT: fcvtzs x10, s0
-; CHECK-GI-CVT-NEXT: cmp x9, x11
-; CHECK-GI-CVT-NEXT: csel x1, x9, x11, gt
-; CHECK-GI-CVT-NEXT: cmp x12, x8
-; CHECK-GI-CVT-NEXT: csel x9, x12, x8, lt
-; CHECK-GI-CVT-NEXT: cmp x9, x11
-; CHECK-GI-CVT-NEXT: csel x2, x9, x11, gt
-; CHECK-GI-CVT-NEXT: cmp x10, x8
-; CHECK-GI-CVT-NEXT: csel x8, x10, x8, lt
-; CHECK-GI-CVT-NEXT: cmp x8, x11
-; CHECK-GI-CVT-NEXT: csel x3, x8, x11, gt
-; CHECK-GI-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_signed_v4f16_v4i50:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-CVT-NEXT: mov h3, v0.h[2]
+; CHECK-CVT-NEXT: mov h0, v0.h[3]
+; CHECK-CVT-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvtzs x9, s2
+; CHECK-CVT-NEXT: fcvt s2, h3
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvtzs x10, s1
+; CHECK-CVT-NEXT: cmp x9, x8
+; CHECK-CVT-NEXT: csel x9, x9, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x12, s2
+; CHECK-CVT-NEXT: cmp x9, x11
+; CHECK-CVT-NEXT: csel x0, x9, x11, gt
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: csel x9, x10, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x10, s0
+; CHECK-CVT-NEXT: cmp x9, x11
+; CHECK-CVT-NEXT: csel x1, x9, x11, gt
+; CHECK-CVT-NEXT: cmp x12, x8
+; CHECK-CVT-NEXT: csel x9, x12, x8, lt
+; CHECK-CVT-NEXT: cmp x9, x11
+; CHECK-CVT-NEXT: csel x2, x9, x11, gt
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: csel x8, x10, x8, lt
+; CHECK-CVT-NEXT: cmp x8, x11
+; CHECK-CVT-NEXT: csel x3, x8, x11, gt
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i50:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: fcvtzs x9, h0
-; CHECK-GI-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
-; CHECK-GI-FP16-NEXT: mov h0, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzs x10, h1
-; CHECK-GI-FP16-NEXT: cmp x9, x8
-; CHECK-GI-FP16-NEXT: csel x9, x9, x8, lt
-; CHECK-GI-FP16-NEXT: fcvtzs x12, h2
-; CHECK-GI-FP16-NEXT: cmp x9, x11
-; CHECK-GI-FP16-NEXT: csel x0, x9, x11, gt
-; CHECK-GI-FP16-NEXT: cmp x10, x8
-; CHECK-GI-FP16-NEXT: csel x9, x10, x8, lt
-; CHECK-GI-FP16-NEXT: fcvtzs x10, h0
-; CHECK-GI-FP16-NEXT: cmp x9, x11
-; CHECK-GI-FP16-NEXT: csel x1, x9, x11, gt
-; CHECK-GI-FP16-NEXT: cmp x12, x8
-; CHECK-GI-FP16-NEXT: csel x9, x12, x8, lt
-; CHECK-GI-FP16-NEXT: cmp x9, x11
-; CHECK-GI-FP16-NEXT: csel x2, x9, x11, gt
-; CHECK-GI-FP16-NEXT: cmp x10, x8
-; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
-; CHECK-GI-FP16-NEXT: cmp x8, x11
-; CHECK-GI-FP16-NEXT: csel x3, x8, x11, gt
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v4f16_v4i50:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-NEXT: fcvtzs x9, h0
+; CHECK-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
+; CHECK-FP16-NEXT: mov h0, v0.h[3]
+; CHECK-FP16-NEXT: fcvtzs x10, h1
+; CHECK-FP16-NEXT: cmp x9, x8
+; CHECK-FP16-NEXT: csel x9, x9, x8, lt
+; CHECK-FP16-NEXT: fcvtzs x12, h2
+; CHECK-FP16-NEXT: cmp x9, x11
+; CHECK-FP16-NEXT: csel x0, x9, x11, gt
+; CHECK-FP16-NEXT: cmp x10, x8
+; CHECK-FP16-NEXT: csel x9, x10, x8, lt
+; CHECK-FP16-NEXT: fcvtzs x10, h0
+; CHECK-FP16-NEXT: cmp x9, x11
+; CHECK-FP16-NEXT: csel x1, x9, x11, gt
+; CHECK-FP16-NEXT: cmp x12, x8
+; CHECK-FP16-NEXT: csel x9, x12, x8, lt
+; CHECK-FP16-NEXT: cmp x9, x11
+; CHECK-FP16-NEXT: csel x2, x9, x11, gt
+; CHECK-FP16-NEXT: cmp x10, x8
+; CHECK-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x3, x8, x11, gt
+; CHECK-FP16-NEXT: ret
%x = call <4 x i50> @llvm.fptosi.sat.v4f16.v4i50(<4 x half> %f)
ret <4 x i50> %x
}
@@ -3556,15 +3443,15 @@ define <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_signed_v8f16_v8i1:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: movi v1.2d, #0000000000000000
-; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: movi v2.2d, #0xffffffffffffffff
-; CHECK-SD-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-SD-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-SD-FP16-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v8f16_v8i1:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: movi v1.2d, #0000000000000000
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: movi v2.2d, #0xffffffffffffffff
+; CHECK-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i1:
; CHECK-GI-CVT: // %bb.0:
@@ -3581,16 +3468,6 @@ define <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-GI-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i1:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: movi v2.2d, #0xffffffffffffffff
-; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x
}
@@ -3663,14 +3540,14 @@ define <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: uzp1 v0.8h, v0.8h, v2.8h
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_signed_v8f16_v8i13:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: mvni v1.8h, #240, lsl #8
-; CHECK-SD-FP16-NEXT: movi v2.8h, #240, lsl #8
-; CHECK-SD-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-SD-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v8f16_v8i13:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: mvni v1.8h, #240, lsl #8
+; CHECK-FP16-NEXT: movi v2.8h, #240, lsl #8
+; CHECK-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i13:
; CHECK-GI-CVT: // %bb.0:
@@ -3686,15 +3563,6 @@ define <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i13:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: mvni v1.8h, #240, lsl #8
-; CHECK-GI-FP16-NEXT: movi v2.8h, #240, lsl #8
-; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i13> @llvm.fptosi.sat.v8f16.v8i13(<8 x half> %f)
ret <8 x i13> %x
}
@@ -3710,10 +3578,10 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: sqxtn2 v0.8h, v1.4s
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_signed_v8f16_v8i16:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v8f16_v8i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i16:
; CHECK-GI-CVT: // %bb.0:
@@ -3729,11 +3597,6 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i16:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x
}
@@ -3785,233 +3648,119 @@ define <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
}
define <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_signed_v8f16_v8i50:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-SD-CVT-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
-; CHECK-SD-CVT-NEXT: mov h2, v1.h[1]
-; CHECK-SD-CVT-NEXT: fcvt s3, h1
-; CHECK-SD-CVT-NEXT: mov h4, v1.h[2]
-; CHECK-SD-CVT-NEXT: mov h1, v1.h[3]
-; CHECK-SD-CVT-NEXT: fcvt s2, h2
-; CHECK-SD-CVT-NEXT: fcvtzs x10, s3
-; CHECK-SD-CVT-NEXT: fcvt s3, h4
-; CHECK-SD-CVT-NEXT: fcvt s1, h1
-; CHECK-SD-CVT-NEXT: fcvtzs x11, s2
-; CHECK-SD-CVT-NEXT: cmp x10, x8
-; CHECK-SD-CVT-NEXT: fcvtzs x12, s3
-; CHECK-SD-CVT-NEXT: csel x10, x10, x8, lt
-; CHECK-SD-CVT-NEXT: mov h2, v0.h[1]
-; CHECK-SD-CVT-NEXT: fcvt s3, h0
-; CHECK-SD-CVT-NEXT: cmp x10, x9
-; CHECK-SD-CVT-NEXT: csel x4, x10, x9, gt
-; CHECK-SD-CVT-NEXT: cmp x11, x8
-; CHECK-SD-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-SD-CVT-NEXT: fcvtzs x11, s1
-; CHECK-SD-CVT-NEXT: mov h1, v0.h[2]
-; CHECK-SD-CVT-NEXT: cmp x10, x9
-; CHECK-SD-CVT-NEXT: fcvt s2, h2
-; CHECK-SD-CVT-NEXT: mov h0, v0.h[3]
-; CHECK-SD-CVT-NEXT: csel x5, x10, x9, gt
-; CHECK-SD-CVT-NEXT: cmp x12, x8
-; CHECK-SD-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-SD-CVT-NEXT: fcvtzs x12, s3
-; CHECK-SD-CVT-NEXT: cmp x10, x9
-; CHECK-SD-CVT-NEXT: fcvt s1, h1
-; CHECK-SD-CVT-NEXT: csel x6, x10, x9, gt
-; CHECK-SD-CVT-NEXT: cmp x11, x8
-; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-SD-CVT-NEXT: fcvtzs x11, s2
-; CHECK-SD-CVT-NEXT: cmp x10, x9
-; CHECK-SD-CVT-NEXT: csel x7, x10, x9, gt
-; CHECK-SD-CVT-NEXT: cmp x12, x8
-; CHECK-SD-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-SD-CVT-NEXT: fcvtzs x12, s1
-; CHECK-SD-CVT-NEXT: cmp x10, x9
-; CHECK-SD-CVT-NEXT: csel x0, x10, x9, gt
-; CHECK-SD-CVT-NEXT: cmp x11, x8
-; CHECK-SD-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-SD-CVT-NEXT: fcvtzs x11, s0
-; CHECK-SD-CVT-NEXT: cmp x10, x9
-; CHECK-SD-CVT-NEXT: csel x1, x10, x9, gt
-; CHECK-SD-CVT-NEXT: cmp x12, x8
-; CHECK-SD-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-SD-CVT-NEXT: cmp x10, x9
-; CHECK-SD-CVT-NEXT: csel x2, x10, x9, gt
-; CHECK-SD-CVT-NEXT: cmp x11, x8
-; CHECK-SD-CVT-NEXT: csel x8, x11, x8, lt
-; CHECK-SD-CVT-NEXT: cmp x8, x9
-; CHECK-SD-CVT-NEXT: csel x3, x8, x9, gt
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_signed_v8f16_v8i50:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-SD-FP16-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
-; CHECK-SD-FP16-NEXT: mov h2, v1.h[1]
-; CHECK-SD-FP16-NEXT: fcvtzs x10, h1
-; CHECK-SD-FP16-NEXT: mov h3, v1.h[2]
-; CHECK-SD-FP16-NEXT: mov h1, v1.h[3]
-; CHECK-SD-FP16-NEXT: fcvtzs x11, h2
-; CHECK-SD-FP16-NEXT: cmp x10, x8
-; CHECK-SD-FP16-NEXT: fcvtzs x12, h3
-; CHECK-SD-FP16-NEXT: csel x10, x10, x8, lt
-; CHECK-SD-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-SD-FP16-NEXT: cmp x10, x9
-; CHECK-SD-FP16-NEXT: csel x4, x10, x9, gt
-; CHECK-SD-FP16-NEXT: cmp x11, x8
-; CHECK-SD-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-SD-FP16-NEXT: fcvtzs x11, h1
-; CHECK-SD-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-SD-FP16-NEXT: cmp x10, x9
-; CHECK-SD-FP16-NEXT: csel x5, x10, x9, gt
-; CHECK-SD-FP16-NEXT: cmp x12, x8
-; CHECK-SD-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-SD-FP16-NEXT: fcvtzs x12, h0
-; CHECK-SD-FP16-NEXT: mov h0, v0.h[3]
-; CHECK-SD-FP16-NEXT: cmp x10, x9
-; CHECK-SD-FP16-NEXT: csel x6, x10, x9, gt
-; CHECK-SD-FP16-NEXT: cmp x11, x8
-; CHECK-SD-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-SD-FP16-NEXT: fcvtzs x11, h1
-; CHECK-SD-FP16-NEXT: cmp x10, x9
-; CHECK-SD-FP16-NEXT: csel x7, x10, x9, gt
-; CHECK-SD-FP16-NEXT: cmp x12, x8
-; CHECK-SD-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-SD-FP16-NEXT: fcvtzs x12, h2
-; CHECK-SD-FP16-NEXT: cmp x10, x9
-; CHECK-SD-FP16-NEXT: csel x0, x10, x9, gt
-; CHECK-SD-FP16-NEXT: cmp x11, x8
-; CHECK-SD-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-SD-FP16-NEXT: fcvtzs x11, h0
-; CHECK-SD-FP16-NEXT: cmp x10, x9
-; CHECK-SD-FP16-NEXT: csel x1, x10, x9, gt
-; CHECK-SD-FP16-NEXT: cmp x12, x8
-; CHECK-SD-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-SD-FP16-NEXT: cmp x10, x9
-; CHECK-SD-FP16-NEXT: csel x2, x10, x9, gt
-; CHECK-SD-FP16-NEXT: cmp x11, x8
-; CHECK-SD-FP16-NEXT: csel x8, x11, x8, lt
-; CHECK-SD-FP16-NEXT: cmp x8, x9
-; CHECK-SD-FP16-NEXT: csel x3, x8, x9, gt
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i50:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-GI-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-GI-CVT-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
-; CHECK-GI-CVT-NEXT: mov h2, v1.h[1]
-; CHECK-GI-CVT-NEXT: fcvt s3, h1
-; CHECK-GI-CVT-NEXT: mov h4, v1.h[2]
-; CHECK-GI-CVT-NEXT: mov h1, v1.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: fcvtzs x10, s3
-; CHECK-GI-CVT-NEXT: fcvt s3, h4
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvtzs x11, s2
-; CHECK-GI-CVT-NEXT: cmp x10, x8
-; CHECK-GI-CVT-NEXT: fcvtzs x12, s3
-; CHECK-GI-CVT-NEXT: csel x10, x10, x8, lt
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[1]
-; CHECK-GI-CVT-NEXT: fcvt s3, h0
-; CHECK-GI-CVT-NEXT: cmp x10, x9
-; CHECK-GI-CVT-NEXT: csel x4, x10, x9, gt
-; CHECK-GI-CVT-NEXT: cmp x11, x8
-; CHECK-GI-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-GI-CVT-NEXT: fcvtzs x11, s1
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[2]
-; CHECK-GI-CVT-NEXT: cmp x10, x9
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: mov h0, v0.h[3]
-; CHECK-GI-CVT-NEXT: csel x5, x10, x9, gt
-; CHECK-GI-CVT-NEXT: cmp x12, x8
-; CHECK-GI-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-GI-CVT-NEXT: fcvtzs x12, s3
-; CHECK-GI-CVT-NEXT: cmp x10, x9
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: csel x6, x10, x9, gt
-; CHECK-GI-CVT-NEXT: cmp x11, x8
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-GI-CVT-NEXT: fcvtzs x11, s2
-; CHECK-GI-CVT-NEXT: cmp x10, x9
-; CHECK-GI-CVT-NEXT: csel x7, x10, x9, gt
-; CHECK-GI-CVT-NEXT: cmp x12, x8
-; CHECK-GI-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-GI-CVT-NEXT: fcvtzs x12, s1
-; CHECK-GI-CVT-NEXT: cmp x10, x9
-; CHECK-GI-CVT-NEXT: csel x0, x10, x9, gt
-; CHECK-GI-CVT-NEXT: cmp x11, x8
-; CHECK-GI-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-GI-CVT-NEXT: fcvtzs x11, s0
-; CHECK-GI-CVT-NEXT: cmp x10, x9
-; CHECK-GI-CVT-NEXT: csel x1, x10, x9, gt
-; CHECK-GI-CVT-NEXT: cmp x12, x8
-; CHECK-GI-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-GI-CVT-NEXT: cmp x10, x9
-; CHECK-GI-CVT-NEXT: csel x2, x10, x9, gt
-; CHECK-GI-CVT-NEXT: cmp x11, x8
-; CHECK-GI-CVT-NEXT: csel x8, x11, x8, lt
-; CHECK-GI-CVT-NEXT: cmp x8, x9
-; CHECK-GI-CVT-NEXT: csel x3, x8, x9, gt
-; CHECK-GI-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_signed_v8f16_v8i50:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-CVT-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: fcvt s3, h1
+; CHECK-CVT-NEXT: mov h4, v1.h[2]
+; CHECK-CVT-NEXT: mov h1, v1.h[3]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvtzs x10, s3
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvtzs x11, s2
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: fcvtzs x12, s3
+; CHECK-CVT-NEXT: csel x10, x10, x8, lt
+; CHECK-CVT-NEXT: mov h2, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s3, h0
+; CHECK-CVT-NEXT: cmp x10, x9
+; CHECK-CVT-NEXT: csel x4, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x11, x8
+; CHECK-CVT-NEXT: csel x10, x11, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x11, s1
+; CHECK-CVT-NEXT: mov h1, v0.h[2]
+; CHECK-CVT-NEXT: cmp x10, x9
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h0, v0.h[3]
+; CHECK-CVT-NEXT: csel x5, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x12, x8
+; CHECK-CVT-NEXT: csel x10, x12, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x12, s3
+; CHECK-CVT-NEXT: cmp x10, x9
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: csel x6, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x11, x8
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csel x10, x11, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x11, s2
+; CHECK-CVT-NEXT: cmp x10, x9
+; CHECK-CVT-NEXT: csel x7, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x12, x8
+; CHECK-CVT-NEXT: csel x10, x12, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x12, s1
+; CHECK-CVT-NEXT: cmp x10, x9
+; CHECK-CVT-NEXT: csel x0, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x11, x8
+; CHECK-CVT-NEXT: csel x10, x11, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x11, s0
+; CHECK-CVT-NEXT: cmp x10, x9
+; CHECK-CVT-NEXT: csel x1, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x12, x8
+; CHECK-CVT-NEXT: csel x10, x12, x8, lt
+; CHECK-CVT-NEXT: cmp x10, x9
+; CHECK-CVT-NEXT: csel x2, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x11, x8
+; CHECK-CVT-NEXT: csel x8, x11, x8, lt
+; CHECK-CVT-NEXT: cmp x8, x9
+; CHECK-CVT-NEXT: csel x3, x8, x9, gt
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i50:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-GI-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-GI-FP16-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
-; CHECK-GI-FP16-NEXT: mov h2, v1.h[1]
-; CHECK-GI-FP16-NEXT: fcvtzs x10, h1
-; CHECK-GI-FP16-NEXT: mov h3, v1.h[2]
-; CHECK-GI-FP16-NEXT: mov h1, v1.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzs x11, h2
-; CHECK-GI-FP16-NEXT: cmp x10, x8
-; CHECK-GI-FP16-NEXT: fcvtzs x12, h3
-; CHECK-GI-FP16-NEXT: csel x10, x10, x8, lt
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: cmp x10, x9
-; CHECK-GI-FP16-NEXT: csel x4, x10, x9, gt
-; CHECK-GI-FP16-NEXT: cmp x11, x8
-; CHECK-GI-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-GI-FP16-NEXT: fcvtzs x11, h1
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: cmp x10, x9
-; CHECK-GI-FP16-NEXT: csel x5, x10, x9, gt
-; CHECK-GI-FP16-NEXT: cmp x12, x8
-; CHECK-GI-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-GI-FP16-NEXT: fcvtzs x12, h0
-; CHECK-GI-FP16-NEXT: mov h0, v0.h[3]
-; CHECK-GI-FP16-NEXT: cmp x10, x9
-; CHECK-GI-FP16-NEXT: csel x6, x10, x9, gt
-; CHECK-GI-FP16-NEXT: cmp x11, x8
-; CHECK-GI-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-GI-FP16-NEXT: fcvtzs x11, h1
-; CHECK-GI-FP16-NEXT: cmp x10, x9
-; CHECK-GI-FP16-NEXT: csel x7, x10, x9, gt
-; CHECK-GI-FP16-NEXT: cmp x12, x8
-; CHECK-GI-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-GI-FP16-NEXT: fcvtzs x12, h2
-; CHECK-GI-FP16-NEXT: cmp x10, x9
-; CHECK-GI-FP16-NEXT: csel x0, x10, x9, gt
-; CHECK-GI-FP16-NEXT: cmp x11, x8
-; CHECK-GI-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-GI-FP16-NEXT: fcvtzs x11, h0
-; CHECK-GI-FP16-NEXT: cmp x10, x9
-; CHECK-GI-FP16-NEXT: csel x1, x10, x9, gt
-; CHECK-GI-FP16-NEXT: cmp x12, x8
-; CHECK-GI-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-GI-FP16-NEXT: cmp x10, x9
-; CHECK-GI-FP16-NEXT: csel x2, x10, x9, gt
-; CHECK-GI-FP16-NEXT: cmp x11, x8
-; CHECK-GI-FP16-NEXT: csel x8, x11, x8, lt
-; CHECK-GI-FP16-NEXT: cmp x8, x9
-; CHECK-GI-FP16-NEXT: csel x3, x8, x9, gt
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v8f16_v8i50:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-FP16-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
+; CHECK-FP16-NEXT: mov h2, v1.h[1]
+; CHECK-FP16-NEXT: fcvtzs x10, h1
+; CHECK-FP16-NEXT: mov h3, v1.h[2]
+; CHECK-FP16-NEXT: mov h1, v1.h[3]
+; CHECK-FP16-NEXT: fcvtzs x11, h2
+; CHECK-FP16-NEXT: cmp x10, x8
+; CHECK-FP16-NEXT: fcvtzs x12, h3
+; CHECK-FP16-NEXT: csel x10, x10, x8, lt
+; CHECK-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-NEXT: cmp x10, x9
+; CHECK-FP16-NEXT: csel x4, x10, x9, gt
+; CHECK-FP16-NEXT: cmp x11, x8
+; CHECK-FP16-NEXT: csel x10, x11, x8, lt
+; CHECK-FP16-NEXT: fcvtzs x11, h1
+; CHECK-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-NEXT: cmp x10, x9
+; CHECK-FP16-NEXT: csel x5, x10, x9, gt
+; CHECK-FP16-NEXT: cmp x12, x8
+; CHECK-FP16-NEXT: csel x10, x12, x8, lt
+; CHECK-FP16-NEXT: fcvtzs x12, h0
+; CHECK-FP16-NEXT: mov h0, v0.h[3]
+; CHECK-FP16-NEXT: cmp x10, x9
+; CHECK-FP16-NEXT: csel x6, x10, x9, gt
+; CHECK-FP16-NEXT: cmp x11, x8
+; CHECK-FP16-NEXT: csel x10, x11, x8, lt
+; CHECK-FP16-NEXT: fcvtzs x11, h1
+; CHECK-FP16-NEXT: cmp x10, x9
+; CHECK-FP16-NEXT: csel x7, x10, x9, gt
+; CHECK-FP16-NEXT: cmp x12, x8
+; CHECK-FP16-NEXT: csel x10, x12, x8, lt
+; CHECK-FP16-NEXT: fcvtzs x12, h2
+; CHECK-FP16-NEXT: cmp x10, x9
+; CHECK-FP16-NEXT: csel x0, x10, x9, gt
+; CHECK-FP16-NEXT: cmp x11, x8
+; CHECK-FP16-NEXT: csel x10, x11, x8, lt
+; CHECK-FP16-NEXT: fcvtzs x11, h0
+; CHECK-FP16-NEXT: cmp x10, x9
+; CHECK-FP16-NEXT: csel x1, x10, x9, gt
+; CHECK-FP16-NEXT: cmp x12, x8
+; CHECK-FP16-NEXT: csel x10, x12, x8, lt
+; CHECK-FP16-NEXT: cmp x10, x9
+; CHECK-FP16-NEXT: csel x2, x10, x9, gt
+; CHECK-FP16-NEXT: cmp x11, x8
+; CHECK-FP16-NEXT: csel x8, x11, x8, lt
+; CHECK-FP16-NEXT: cmp x8, x9
+; CHECK-FP16-NEXT: csel x3, x8, x9, gt
+; CHECK-FP16-NEXT: ret
%x = call <8 x i50> @llvm.fptosi.sat.v8f16.v8i50(<8 x half> %f)
ret <8 x i50> %x
}
@@ -4835,11 +4584,11 @@ define <16 x i16> @test_signed_v16f16_v16i16(<16 x half> %f) {
; CHECK-SD-CVT-NEXT: sqxtn2 v1.8h, v3.4s
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_signed_v16f16_v16i16:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: fcvtzs v1.8h, v1.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_signed_v16f16_v16i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: fcvtzs v1.8h, v1.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_signed_v16f16_v16i16:
; CHECK-GI-CVT: // %bb.0:
@@ -4864,12 +4613,6 @@ define <16 x i16> @test_signed_v16f16_v16i16(<16 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v3.8h, v1.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_signed_v16f16_v16i16:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: fcvtzs v1.8h, v1.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <16 x i16> @llvm.fptosi.sat.v16f16.v16i16(<16 x half> %f)
ret <16 x i16> %x
}
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 1b3a8a3b70e13..4053d56b88545 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-CVT
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
-; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-CVT,CHECK-SD-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-FP16,CHECK-SD-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-CVT,CHECK-GI-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-FP16,CHECK-GI-FP16
; CHECK-GI: warning: Instruction selection used fallback path for test_unsigned_v4f32_v4i50
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_unsigned_v4f16_v4i50
@@ -993,31 +993,18 @@ declare <7 x i32> @llvm.fptoui.sat.v7f16.v7i32 (<7 x half>)
declare <8 x i32> @llvm.fptoui.sat.v8f16.v8i32 (<8 x half>)
define <1 x i32> @test_unsigned_v1f16_v1i32(<1 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_unsigned_v1f16_v1i32:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: fcvtzu w8, s0
-; CHECK-SD-CVT-NEXT: fmov s0, w8
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_unsigned_v1f16_v1i32:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu w8, h0
-; CHECK-SD-FP16-NEXT: fmov s0, w8
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-CVT-LABEL: test_unsigned_v1f16_v1i32:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvtzu w8, s0
+; CHECK-CVT-NEXT: fmov s0, w8
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_unsigned_v1f16_v1i32:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: fcvtzu w8, s0
-; CHECK-GI-CVT-NEXT: fmov s0, w8
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v1f16_v1i32:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu w8, h0
-; CHECK-GI-FP16-NEXT: fmov s0, w8
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v1f16_v1i32:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu w8, h0
+; CHECK-FP16-NEXT: fmov s0, w8
+; CHECK-FP16-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f16.v1i32(<1 x half> %f)
ret <1 x i32> %x
}
@@ -2338,109 +2325,61 @@ declare <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half>)
declare <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half>)
define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i1:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-CVT-NEXT: movi v1.4s, #1
-; CHECK-SD-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-SD-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i1:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: movi v1.4h, #1
-; CHECK-SD-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-SD-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i1:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #1
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i1:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-NEXT: movi v1.4s, #1
+; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i1:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v1.4h, #1
-; CHECK-GI-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-GI-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i1:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: movi v1.4h, #1
+; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h
+; CHECK-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT: ret
%x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x
}
define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i8:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-CVT-NEXT: movi v1.2d, #0x0000ff000000ff
-; CHECK-SD-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-SD-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i8:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: movi d1, #0xff00ff00ff00ff
-; CHECK-SD-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-SD-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i8:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-NEXT: movi v1.2d, #0x0000ff000000ff
+; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i8:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.2d, #0x0000ff000000ff
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i8:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi d1, #0xff00ff00ff00ff
-; CHECK-GI-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-GI-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i8:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: movi d1, #0xff00ff00ff00ff
+; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h
+; CHECK-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT: ret
%x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x
}
define <4 x i13> @test_unsigned_v4f16_v4i13(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i13:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-SD-CVT-NEXT: movi v1.4s, #31, msl #8
-; CHECK-SD-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-SD-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i13:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-NEXT: movi v1.4s, #31, msl #8
+; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i13:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-SD-FP16-NEXT: mvni v1.4h, #224, lsl #8
-; CHECK-SD-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i13:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #31, msl #8
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i13:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-GI-FP16-NEXT: mvni v1.4h, #224, lsl #8
-; CHECK-GI-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i13:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h
+; CHECK-FP16-NEXT: mvni v1.4h, #224, lsl #8
+; CHECK-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT: ret
%x = call <4 x i13> @llvm.fptoui.sat.v4f16.v4i13(<4 x half> %f)
ret <4 x i13> %x
}
@@ -2453,10 +2392,10 @@ define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
; CHECK-SD-CVT-NEXT: uqxtn v0.4h, v0.4s
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i16:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i16:
; CHECK-GI-CVT: // %bb.0:
@@ -2466,11 +2405,6 @@ define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i16:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i16> @llvm.fptoui.sat.v4f16.v4i16(<4 x half> %f)
ret <4 x i16> %x
}
@@ -2498,97 +2432,51 @@ define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
}
define <4 x i50> @test_unsigned_v4f16_v4i50(<4 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i50:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-SD-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-SD-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-SD-CVT-NEXT: mov h3, v0.h[3]
-; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: fcvt s1, h1
-; CHECK-SD-CVT-NEXT: fcvt s2, h2
-; CHECK-SD-CVT-NEXT: fcvt s3, h3
-; CHECK-SD-CVT-NEXT: fcvtzu x9, s0
-; CHECK-SD-CVT-NEXT: fcvtzu x10, s1
-; CHECK-SD-CVT-NEXT: fcvtzu x11, s2
-; CHECK-SD-CVT-NEXT: fcvtzu x12, s3
-; CHECK-SD-CVT-NEXT: cmp x9, x8
-; CHECK-SD-CVT-NEXT: csel x0, x9, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x10, x8
-; CHECK-SD-CVT-NEXT: csel x1, x10, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x11, x8
-; CHECK-SD-CVT-NEXT: csel x2, x11, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x12, x8
-; CHECK-SD-CVT-NEXT: csel x3, x12, x8, lo
-; CHECK-SD-CVT-NEXT: ret
+; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i50:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
+; CHECK-CVT-NEXT: mov h3, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvtzu x9, s0
+; CHECK-CVT-NEXT: fcvtzu x10, s1
+; CHECK-CVT-NEXT: fcvtzu x11, s2
+; CHECK-CVT-NEXT: fcvtzu x12, s3
+; CHECK-CVT-NEXT: cmp x9, x8
+; CHECK-CVT-NEXT: csel x0, x9, x8, lo
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: csel x1, x10, x8, lo
+; CHECK-CVT-NEXT: cmp x11, x8
+; CHECK-CVT-NEXT: csel x2, x11, x8, lo
+; CHECK-CVT-NEXT: cmp x12, x8
+; CHECK-CVT-NEXT: csel x3, x12, x8, lo
+; CHECK-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i50:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-SD-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-SD-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-SD-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-SD-FP16-NEXT: fcvtzu x9, h0
-; CHECK-SD-FP16-NEXT: fcvtzu x10, h1
-; CHECK-SD-FP16-NEXT: fcvtzu x11, h2
-; CHECK-SD-FP16-NEXT: fcvtzu x12, h3
-; CHECK-SD-FP16-NEXT: cmp x9, x8
-; CHECK-SD-FP16-NEXT: csel x0, x9, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x10, x8
-; CHECK-SD-FP16-NEXT: csel x1, x10, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x11, x8
-; CHECK-SD-FP16-NEXT: csel x2, x11, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x12, x8
-; CHECK-SD-FP16-NEXT: csel x3, x12, x8, lo
-; CHECK-SD-FP16-NEXT: ret
-;
-; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i50:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvtzu x9, s0
-; CHECK-GI-CVT-NEXT: fcvtzu x10, s1
-; CHECK-GI-CVT-NEXT: fcvtzu x11, s2
-; CHECK-GI-CVT-NEXT: fcvtzu x12, s3
-; CHECK-GI-CVT-NEXT: cmp x9, x8
-; CHECK-GI-CVT-NEXT: csel x0, x9, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x10, x8
-; CHECK-GI-CVT-NEXT: csel x1, x10, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x11, x8
-; CHECK-GI-CVT-NEXT: csel x2, x11, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x12, x8
-; CHECK-GI-CVT-NEXT: csel x3, x12, x8, lo
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i50:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzu x9, h0
-; CHECK-GI-FP16-NEXT: fcvtzu x10, h1
-; CHECK-GI-FP16-NEXT: fcvtzu x11, h2
-; CHECK-GI-FP16-NEXT: fcvtzu x12, h3
-; CHECK-GI-FP16-NEXT: cmp x9, x8
-; CHECK-GI-FP16-NEXT: csel x0, x9, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x10, x8
-; CHECK-GI-FP16-NEXT: csel x1, x10, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x11, x8
-; CHECK-GI-FP16-NEXT: csel x2, x11, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x12, x8
-; CHECK-GI-FP16-NEXT: csel x3, x12, x8, lo
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i50:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
+; CHECK-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-NEXT: fcvtzu x9, h0
+; CHECK-FP16-NEXT: fcvtzu x10, h1
+; CHECK-FP16-NEXT: fcvtzu x11, h2
+; CHECK-FP16-NEXT: fcvtzu x12, h3
+; CHECK-FP16-NEXT: cmp x9, x8
+; CHECK-FP16-NEXT: csel x0, x9, x8, lo
+; CHECK-FP16-NEXT: cmp x10, x8
+; CHECK-FP16-NEXT: csel x1, x10, x8, lo
+; CHECK-FP16-NEXT: cmp x11, x8
+; CHECK-FP16-NEXT: csel x2, x11, x8, lo
+; CHECK-FP16-NEXT: cmp x12, x8
+; CHECK-FP16-NEXT: csel x3, x12, x8, lo
+; CHECK-FP16-NEXT: ret
%x = call <4 x i50> @llvm.fptoui.sat.v4f16.v4i50(<4 x half> %f)
ret <4 x i50> %x
}
@@ -2924,13 +2812,13 @@ define <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i1:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: movi v1.8h, #1
-; CHECK-SD-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
-; CHECK-SD-FP16-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i1:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: movi v1.8h, #1
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i1:
; CHECK-GI-CVT: // %bb.0:
@@ -2944,14 +2832,6 @@ define <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i1:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v1.8h, #1
-; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x
}
@@ -3013,12 +2893,12 @@ define <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: uzp1 v0.8h, v0.8h, v2.8h
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i13:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: mvni v1.8h, #224, lsl #8
-; CHECK-SD-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i13:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: mvni v1.8h, #224, lsl #8
+; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i13:
; CHECK-GI-CVT: // %bb.0:
@@ -3031,13 +2911,6 @@ define <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i13:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: mvni v1.8h, #224, lsl #8
-; CHECK-GI-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i13> @llvm.fptoui.sat.v8f16.v8i13(<8 x half> %f)
ret <8 x i13> %x
}
@@ -3053,10 +2926,10 @@ define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
; CHECK-SD-CVT-NEXT: uqxtn2 v0.8h, v1.4s
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i16:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i16:
; CHECK-GI-CVT: // %bb.0:
@@ -3069,11 +2942,6 @@ define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i16:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x
}
@@ -3122,165 +2990,85 @@ define <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) {
}
define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
-; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i50:
-; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-CVT-NEXT: mov h5, v0.h[1]
-; CHECK-SD-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-SD-CVT-NEXT: mov h6, v0.h[2]
-; CHECK-SD-CVT-NEXT: mov h7, v0.h[3]
-; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: mov h2, v1.h[1]
-; CHECK-SD-CVT-NEXT: mov h3, v1.h[2]
-; CHECK-SD-CVT-NEXT: mov h4, v1.h[3]
-; CHECK-SD-CVT-NEXT: fcvt s1, h1
-; CHECK-SD-CVT-NEXT: fcvtzu x13, s0
-; CHECK-SD-CVT-NEXT: fcvt s2, h2
-; CHECK-SD-CVT-NEXT: fcvt s3, h3
-; CHECK-SD-CVT-NEXT: fcvt s4, h4
-; CHECK-SD-CVT-NEXT: fcvtzu x9, s1
-; CHECK-SD-CVT-NEXT: fcvt s1, h5
-; CHECK-SD-CVT-NEXT: fcvtzu x10, s2
-; CHECK-SD-CVT-NEXT: fcvtzu x11, s3
-; CHECK-SD-CVT-NEXT: fcvt s2, h6
-; CHECK-SD-CVT-NEXT: fcvtzu x12, s4
-; CHECK-SD-CVT-NEXT: fcvt s3, h7
-; CHECK-SD-CVT-NEXT: cmp x9, x8
-; CHECK-SD-CVT-NEXT: fcvtzu x14, s1
-; CHECK-SD-CVT-NEXT: csel x4, x9, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x10, x8
-; CHECK-SD-CVT-NEXT: fcvtzu x9, s2
-; CHECK-SD-CVT-NEXT: csel x5, x10, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x11, x8
-; CHECK-SD-CVT-NEXT: fcvtzu x10, s3
-; CHECK-SD-CVT-NEXT: csel x6, x11, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x12, x8
-; CHECK-SD-CVT-NEXT: csel x7, x12, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x13, x8
-; CHECK-SD-CVT-NEXT: csel x0, x13, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x14, x8
-; CHECK-SD-CVT-NEXT: csel x1, x14, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x9, x8
-; CHECK-SD-CVT-NEXT: csel x2, x9, x8, lo
-; CHECK-SD-CVT-NEXT: cmp x10, x8
-; CHECK-SD-CVT-NEXT: csel x3, x10, x8, lo
-; CHECK-SD-CVT-NEXT: ret
-;
-; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i50:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-SD-FP16-NEXT: fcvtzu x13, h0
-; CHECK-SD-FP16-NEXT: mov h2, v1.h[1]
-; CHECK-SD-FP16-NEXT: mov h3, v1.h[2]
-; CHECK-SD-FP16-NEXT: mov h4, v1.h[3]
-; CHECK-SD-FP16-NEXT: fcvtzu x9, h1
-; CHECK-SD-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-SD-FP16-NEXT: fcvtzu x10, h2
-; CHECK-SD-FP16-NEXT: fcvtzu x11, h3
-; CHECK-SD-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-SD-FP16-NEXT: fcvtzu x12, h4
-; CHECK-SD-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-SD-FP16-NEXT: cmp x9, x8
-; CHECK-SD-FP16-NEXT: fcvtzu x14, h1
-; CHECK-SD-FP16-NEXT: csel x4, x9, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x10, x8
-; CHECK-SD-FP16-NEXT: fcvtzu x9, h2
-; CHECK-SD-FP16-NEXT: csel x5, x10, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x11, x8
-; CHECK-SD-FP16-NEXT: fcvtzu x10, h3
-; CHECK-SD-FP16-NEXT: csel x6, x11, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x12, x8
-; CHECK-SD-FP16-NEXT: csel x7, x12, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x13, x8
-; CHECK-SD-FP16-NEXT: csel x0, x13, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x14, x8
-; CHECK-SD-FP16-NEXT: csel x1, x14, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x9, x8
-; CHECK-SD-FP16-NEXT: csel x2, x9, x8, lo
-; CHECK-SD-FP16-NEXT: cmp x10, x8
-; CHECK-SD-FP16-NEXT: csel x3, x10, x8, lo
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i50:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-CVT-NEXT: mov h5, v0.h[1]
+; CHECK-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
+; CHECK-CVT-NEXT: mov h6, v0.h[2]
+; CHECK-CVT-NEXT: mov h7, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvtzu x13, s0
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h4
+; CHECK-CVT-NEXT: fcvtzu x9, s1
+; CHECK-CVT-NEXT: fcvt s1, h5
+; CHECK-CVT-NEXT: fcvtzu x10, s2
+; CHECK-CVT-NEXT: fcvtzu x11, s3
+; CHECK-CVT-NEXT: fcvt s2, h6
+; CHECK-CVT-NEXT: fcvtzu x12, s4
+; CHECK-CVT-NEXT: fcvt s3, h7
+; CHECK-CVT-NEXT: cmp x9, x8
+; CHECK-CVT-NEXT: fcvtzu x14, s1
+; CHECK-CVT-NEXT: csel x4, x9, x8, lo
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: fcvtzu x9, s2
+; CHECK-CVT-NEXT: csel x5, x10, x8, lo
+; CHECK-CVT-NEXT: cmp x11, x8
+; CHECK-CVT-NEXT: fcvtzu x10, s3
+; CHECK-CVT-NEXT: csel x6, x11, x8, lo
+; CHECK-CVT-NEXT: cmp x12, x8
+; CHECK-CVT-NEXT: csel x7, x12, x8, lo
+; CHECK-CVT-NEXT: cmp x13, x8
+; CHECK-CVT-NEXT: csel x0, x13, x8, lo
+; CHECK-CVT-NEXT: cmp x14, x8
+; CHECK-CVT-NEXT: csel x1, x14, x8, lo
+; CHECK-CVT-NEXT: cmp x9, x8
+; CHECK-CVT-NEXT: csel x2, x9, x8, lo
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: csel x3, x10, x8, lo
+; CHECK-CVT-NEXT: ret
;
-; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i50:
-; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-GI-CVT-NEXT: mov h5, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-GI-CVT-NEXT: mov h6, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov h7, v0.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov h2, v1.h[1]
-; CHECK-GI-CVT-NEXT: mov h3, v1.h[2]
-; CHECK-GI-CVT-NEXT: mov h4, v1.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvtzu x13, s0
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvt s4, h4
-; CHECK-GI-CVT-NEXT: fcvtzu x9, s1
-; CHECK-GI-CVT-NEXT: fcvt s1, h5
-; CHECK-GI-CVT-NEXT: fcvtzu x10, s2
-; CHECK-GI-CVT-NEXT: fcvtzu x11, s3
-; CHECK-GI-CVT-NEXT: fcvt s2, h6
-; CHECK-GI-CVT-NEXT: fcvtzu x12, s4
-; CHECK-GI-CVT-NEXT: fcvt s3, h7
-; CHECK-GI-CVT-NEXT: cmp x9, x8
-; CHECK-GI-CVT-NEXT: fcvtzu x14, s1
-; CHECK-GI-CVT-NEXT: csel x4, x9, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x10, x8
-; CHECK-GI-CVT-NEXT: fcvtzu x9, s2
-; CHECK-GI-CVT-NEXT: csel x5, x10, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x11, x8
-; CHECK-GI-CVT-NEXT: fcvtzu x10, s3
-; CHECK-GI-CVT-NEXT: csel x6, x11, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x12, x8
-; CHECK-GI-CVT-NEXT: csel x7, x12, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x13, x8
-; CHECK-GI-CVT-NEXT: csel x0, x13, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x14, x8
-; CHECK-GI-CVT-NEXT: csel x1, x14, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x9, x8
-; CHECK-GI-CVT-NEXT: csel x2, x9, x8, lo
-; CHECK-GI-CVT-NEXT: cmp x10, x8
-; CHECK-GI-CVT-NEXT: csel x3, x10, x8, lo
-; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i50:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-GI-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
-; CHECK-GI-FP16-NEXT: fcvtzu x13, h0
-; CHECK-GI-FP16-NEXT: mov h2, v1.h[1]
-; CHECK-GI-FP16-NEXT: mov h3, v1.h[2]
-; CHECK-GI-FP16-NEXT: mov h4, v1.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzu x9, h1
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: fcvtzu x10, h2
-; CHECK-GI-FP16-NEXT: fcvtzu x11, h3
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: fcvtzu x12, h4
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: cmp x9, x8
-; CHECK-GI-FP16-NEXT: fcvtzu x14, h1
-; CHECK-GI-FP16-NEXT: csel x4, x9, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x10, x8
-; CHECK-GI-FP16-NEXT: fcvtzu x9, h2
-; CHECK-GI-FP16-NEXT: csel x5, x10, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x11, x8
-; CHECK-GI-FP16-NEXT: fcvtzu x10, h3
-; CHECK-GI-FP16-NEXT: csel x6, x11, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x12, x8
-; CHECK-GI-FP16-NEXT: csel x7, x12, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x13, x8
-; CHECK-GI-FP16-NEXT: csel x0, x13, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x14, x8
-; CHECK-GI-FP16-NEXT: csel x1, x14, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x9, x8
-; CHECK-GI-FP16-NEXT: csel x2, x9, x8, lo
-; CHECK-GI-FP16-NEXT: cmp x10, x8
-; CHECK-GI-FP16-NEXT: csel x3, x10, x8, lo
-; CHECK-GI-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i50:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
+; CHECK-FP16-NEXT: fcvtzu x13, h0
+; CHECK-FP16-NEXT: mov h2, v1.h[1]
+; CHECK-FP16-NEXT: mov h3, v1.h[2]
+; CHECK-FP16-NEXT: mov h4, v1.h[3]
+; CHECK-FP16-NEXT: fcvtzu x9, h1
+; CHECK-FP16-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-NEXT: fcvtzu x10, h2
+; CHECK-FP16-NEXT: fcvtzu x11, h3
+; CHECK-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-NEXT: fcvtzu x12, h4
+; CHECK-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-NEXT: cmp x9, x8
+; CHECK-FP16-NEXT: fcvtzu x14, h1
+; CHECK-FP16-NEXT: csel x4, x9, x8, lo
+; CHECK-FP16-NEXT: cmp x10, x8
+; CHECK-FP16-NEXT: fcvtzu x9, h2
+; CHECK-FP16-NEXT: csel x5, x10, x8, lo
+; CHECK-FP16-NEXT: cmp x11, x8
+; CHECK-FP16-NEXT: fcvtzu x10, h3
+; CHECK-FP16-NEXT: csel x6, x11, x8, lo
+; CHECK-FP16-NEXT: cmp x12, x8
+; CHECK-FP16-NEXT: csel x7, x12, x8, lo
+; CHECK-FP16-NEXT: cmp x13, x8
+; CHECK-FP16-NEXT: csel x0, x13, x8, lo
+; CHECK-FP16-NEXT: cmp x14, x8
+; CHECK-FP16-NEXT: csel x1, x14, x8, lo
+; CHECK-FP16-NEXT: cmp x9, x8
+; CHECK-FP16-NEXT: csel x2, x9, x8, lo
+; CHECK-FP16-NEXT: cmp x10, x8
+; CHECK-FP16-NEXT: csel x3, x10, x8, lo
+; CHECK-FP16-NEXT: ret
%x = call <8 x i50> @llvm.fptoui.sat.v8f16.v8i50(<8 x half> %f)
ret <8 x i50> %x
}
@@ -3998,11 +3786,11 @@ define <16 x i16> @test_unsigned_v16f16_v16i16(<16 x half> %f) {
; CHECK-SD-CVT-NEXT: uqxtn2 v1.8h, v3.4s
; CHECK-SD-CVT-NEXT: ret
;
-; CHECK-SD-FP16-LABEL: test_unsigned_v16f16_v16i16:
-; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-SD-FP16-NEXT: fcvtzu v1.8h, v1.8h
-; CHECK-SD-FP16-NEXT: ret
+; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: fcvtzu v1.8h, v1.8h
+; CHECK-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_v16f16_v16i16:
; CHECK-GI-CVT: // %bb.0:
@@ -4022,12 +3810,6 @@ define <16 x i16> @test_unsigned_v16f16_v16i16(<16 x half> %f) {
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v3.8h, v0.8h
; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v4.8h, v1.8h
; CHECK-GI-CVT-NEXT: ret
-;
-; CHECK-GI-FP16-LABEL: test_unsigned_v16f16_v16i16:
-; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: fcvtzu v1.8h, v1.8h
-; CHECK-GI-FP16-NEXT: ret
%x = call <16 x i16> @llvm.fptoui.sat.v16f16.v16i16(<16 x half> %f)
ret <16 x i16> %x
}
diff --git a/llvm/test/CodeGen/AArch64/qmovn.ll b/llvm/test/CodeGen/AArch64/qmovn.ll
index 2685ea9fb5d20..d24af25903326 100644
--- a/llvm/test/CodeGen/AArch64/qmovn.ll
+++ b/llvm/test/CodeGen/AArch64/qmovn.ll
@@ -1,11 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs -global-isel=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs -global-isel=1 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i16> @vqmovni32_smaxmin(<4 x i32> %s0) {
-; CHECK-LABEL: vqmovni32_smaxmin:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni32_smaxmin:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni32_smaxmin:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.4s, #127, msl #8
+; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
@@ -16,10 +26,19 @@ entry:
}
define <4 x i16> @vqmovni32_sminmax(<4 x i32> %s0) {
-; CHECK-LABEL: vqmovni32_sminmax:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni32_sminmax:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni32_sminmax:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mvni v1.4s, #127, msl #8
+; CHECK-GI-NEXT: movi v2.4s, #127, msl #8
+; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: smin v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
@@ -30,10 +49,17 @@ entry:
}
define <4 x i16> @vqmovni32_umaxmin(<4 x i32> %s0) {
-; CHECK-LABEL: vqmovni32_umaxmin:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni32_umaxmin:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni32_umaxmin:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-GI-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -42,10 +68,19 @@ entry:
}
define <8 x i8> @vqmovni16_smaxmin(<8 x i16> %s0) {
-; CHECK-LABEL: vqmovni16_smaxmin:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.8b, v0.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni16_smaxmin:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni16_smaxmin:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.8h, #127
+; CHECK-GI-NEXT: mvni v2.8h, #127
+; CHECK-GI-NEXT: smin v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: smax v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
@@ -56,10 +91,19 @@ entry:
}
define <8 x i8> @vqmovni16_sminmax(<8 x i16> %s0) {
-; CHECK-LABEL: vqmovni16_sminmax:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.8b, v0.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni16_sminmax:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni16_sminmax:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mvni v1.8h, #127
+; CHECK-GI-NEXT: movi v2.8h, #127
+; CHECK-GI-NEXT: smax v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: smin v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
@@ -70,10 +114,17 @@ entry:
}
define <8 x i8> @vqmovni16_umaxmin(<8 x i16> %s0) {
-; CHECK-LABEL: vqmovni16_umaxmin:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uqxtn v0.8b, v0.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni16_umaxmin:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uqxtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni16_umaxmin:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: umin v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
@@ -82,10 +133,23 @@ entry:
}
define <2 x i32> @vqmovni64_smaxmin(<2 x i64> %s0) {
-; CHECK-LABEL: vqmovni64_smaxmin:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni64_smaxmin:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni64_smaxmin:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI6_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI6_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI6_0
+; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
+; CHECK-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>
@@ -96,10 +160,23 @@ entry:
}
define <2 x i32> @vqmovni64_sminmax(<2 x i64> %s0) {
-; CHECK-LABEL: vqmovni64_sminmax:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni64_sminmax:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni64_sminmax:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI7_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI7_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI7_0
+; CHECK-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
+; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>
@@ -110,10 +187,20 @@ entry:
}
define <2 x i32> @vqmovni64_smaxmin_u(<2 x i64> %s0) {
-; CHECK-LABEL: vqmovni64_smaxmin_u:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni64_smaxmin_u:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni64_smaxmin_u:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, #0
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp slt <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
@@ -124,10 +211,20 @@ entry:
}
define <2 x i32> @vqmovni64_sminmax_u(<2 x i64> %s0) {
-; CHECK-LABEL: vqmovni64_sminmax_u:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni64_sminmax_u:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtun v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni64_sminmax_u:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, #0
+; CHECK-GI-NEXT: movi v2.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: cmgt v1.2d, v2.2d, v0.2d
+; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp sgt <2 x i64> %s0, zeroinitializer
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> zeroinitializer
@@ -138,10 +235,19 @@ entry:
}
define <4 x i16> @vqmovni32_smaxmin_u(<4 x i32> %s0) {
-; CHECK-LABEL: vqmovni32_smaxmin_u:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni32_smaxmin_u:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni32_smaxmin_u:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: smax v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp slt <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -152,10 +258,19 @@ entry:
}
define <4 x i16> @vqmovni32_sminmax_u(<4 x i32> %s0) {
-; CHECK-LABEL: vqmovni32_sminmax_u:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni32_sminmax_u:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni32_sminmax_u:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v2.2d, #0x00ffff0000ffff
+; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: smin v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp sgt <4 x i32> %s0, zeroinitializer
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> zeroinitializer
@@ -166,10 +281,19 @@ entry:
}
define <8 x i8> @vqmovni16_smaxmin_u(<8 x i16> %s0) {
-; CHECK-LABEL: vqmovni16_smaxmin_u:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.8b, v0.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni16_smaxmin_u:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtun v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni16_smaxmin_u:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: smin v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: smax v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp slt <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
@@ -180,10 +304,19 @@ entry:
}
define <8 x i8> @vqmovni16_sminmax_u(<8 x i16> %s0) {
-; CHECK-LABEL: vqmovni16_sminmax_u:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.8b, v0.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni16_sminmax_u:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sqxtun v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni16_sminmax_u:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: smax v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: smin v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp sgt <8 x i16> %s0, zeroinitializer
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> zeroinitializer
@@ -194,10 +327,18 @@ entry:
}
define <2 x i32> @vqmovni64_umaxmin(<2 x i64> %s0) {
-; CHECK-LABEL: vqmovni64_umaxmin:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uqxtn v0.2s, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vqmovni64_umaxmin:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uqxtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqmovni64_umaxmin:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
entry:
%c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
@@ -208,11 +349,21 @@ entry:
; Test the (concat_vectors (X), (trunc(smin(smax(Y, -2^n), 2^n-1))) pattern.
define <16 x i8> @signed_minmax_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-LABEL: signed_minmax_v8i16_to_v16i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtn2 v0.16b, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: signed_minmax_v8i16_to_v16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtn2 v0.16b, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signed_minmax_v8i16_to_v16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8h, #127
+; CHECK-GI-NEXT: mvni v3.8h, #127
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smin v1.8h, v1.8h, v2.8h
+; CHECK-GI-NEXT: smax v1.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
+; CHECK-GI-NEXT: ret
entry:
%min = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %y, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)
%max = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %min, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)
@@ -222,11 +373,21 @@ entry:
}
define <8 x i16> @signed_minmax_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-LABEL: signed_minmax_v4i32_to_v8i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: signed_minmax_v4i32_to_v8i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signed_minmax_v4i32_to_v8i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4s, #127, msl #8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smin v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: mvni v2.4s, #127, msl #8
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%min = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %y, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
%max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %min, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
@@ -236,11 +397,25 @@ entry:
}
define <4 x i32> @signed_minmax_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-LABEL: signed_minmax_v2i64_to_v4i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtn2 v0.4s, v1.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: signed_minmax_v2i64_to_v4i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtn2 v0.4s, v1.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signed_minmax_v2i64_to_v4i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI17_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
+; CHECK-GI-NEXT: ret
entry:
%min = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %y, <2 x i64> <i64 2147483647, i64 2147483647>)
%max = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %min, <2 x i64> <i64 -2147483648, i64 -2147483648>)
@@ -252,11 +427,21 @@ entry:
; Test the (concat_vectors (X), (trunc(smax(smin(Y, 2^n-1), -2^n))) pattern.
define <16 x i8> @signed_maxmin_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-LABEL: signed_maxmin_v8i16_to_v16i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtn2 v0.16b, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: signed_maxmin_v8i16_to_v16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtn2 v0.16b, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signed_maxmin_v8i16_to_v16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mvni v2.8h, #127
+; CHECK-GI-NEXT: movi v3.8h, #127
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smax v1.8h, v1.8h, v2.8h
+; CHECK-GI-NEXT: smin v1.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
+; CHECK-GI-NEXT: ret
entry:
%max = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %y, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)
%min = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %max, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)
@@ -266,11 +451,21 @@ entry:
}
define <8 x i16> @signed_maxmin_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-LABEL: signed_maxmin_v4i32_to_v8i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: signed_maxmin_v4i32_to_v8i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signed_maxmin_v4i32_to_v8i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mvni v2.4s, #127, msl #8
+; CHECK-GI-NEXT: movi v3.4s, #127, msl #8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
%min = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %max, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
@@ -280,11 +475,25 @@ entry:
}
define <4 x i32> @signed_maxmin_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-LABEL: signed_maxmin_v2i64_to_v4i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtn2 v0.4s, v1.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: signed_maxmin_v2i64_to_v4i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtn2 v0.4s, v1.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signed_maxmin_v2i64_to_v4i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI20_1
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI20_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI20_0
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI20_0]
+; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
+; CHECK-GI-NEXT: ret
entry:
%max = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> <i64 -2147483648, i64 -2147483648>)
%min = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %max, <2 x i64> <i64 2147483647, i64 2147483647>)
@@ -296,11 +505,19 @@ entry:
; Test the (concat_vectors (X), (trunc(umin(Y, 2^n)))) pattern.
define <16 x i8> @unsigned_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-LABEL: unsigned_v8i16_to_v16i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: uqxtn2 v0.16b, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: unsigned_v8i16_to_v16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: uqxtn2 v0.16b, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: unsigned_v8i16_to_v16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umin v1.8h, v1.8h, v2.8h
+; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
+; CHECK-GI-NEXT: ret
entry:
%min = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %y, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
%trunc = trunc <8 x i16> %min to <8 x i8>
@@ -309,11 +526,19 @@ entry:
}
define <8 x i16> @unsigned_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-LABEL: unsigned_v4i32_to_v8i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: uqxtn2 v0.8h, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: unsigned_v4i32_to_v8i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: uqxtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: unsigned_v4i32_to_v8i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0x00ffff0000ffff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umin v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%min = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %y, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
%trunc = trunc <4 x i32> %min to <4 x i16>
@@ -322,11 +547,20 @@ entry:
}
define <4 x i32> @unsigned_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-LABEL: unsigned_v2i64_to_v4i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: uqxtn2 v0.4s, v1.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: unsigned_v2i64_to_v4i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: uqxtn2 v0.4s, v1.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: unsigned_v2i64_to_v4i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: cmhi v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
+; CHECK-GI-NEXT: ret
entry:
%min = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %y, <2 x i64> <i64 4294967295, i64 4294967295>)
%trunc = trunc <2 x i64> %min to <2 x i32>
@@ -337,11 +571,21 @@ entry:
; Test the (concat_vectors (X), (trunc(umin(smax(Y, 0), 2^n))))) pattern.
define <16 x i8> @us_maxmin_v8i16_to_v16i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-LABEL: us_maxmin_v8i16_to_v16i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtun2 v0.16b, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: us_maxmin_v8i16_to_v16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtun2 v0.16b, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: us_maxmin_v8i16_to_v16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v3.2d, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smax v1.8h, v1.8h, v2.8h
+; CHECK-GI-NEXT: umin v1.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
+; CHECK-GI-NEXT: ret
entry:
%max = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %y, <8 x i16> zeroinitializer)
%min = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %max, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
@@ -351,11 +595,21 @@ entry:
}
define <8 x i16> @us_maxmin_v4i32_to_v8i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-LABEL: us_maxmin_v4i32_to_v8i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtun2 v0.8h, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: us_maxmin_v4i32_to_v8i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtun2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: us_maxmin_v4i32_to_v8i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v3.2d, #0x00ffff0000ffff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: umin v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%max = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> zeroinitializer)
%min = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %max, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -365,11 +619,22 @@ entry:
}
define <4 x i32> @us_maxmin_v2i64_to_v4i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-LABEL: us_maxmin_v2i64_to_v4i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtun2 v0.4s, v1.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: us_maxmin_v2i64_to_v4i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtun2 v0.4s, v1.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: us_maxmin_v2i64_to_v4i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, #0
+; CHECK-GI-NEXT: movi v3.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: cmhi v2.2d, v3.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
+; CHECK-GI-NEXT: ret
entry:
%max = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> zeroinitializer)
%min = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %max, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -381,11 +646,21 @@ entry:
; Test the (concat_vectors (X), (trunc(smin(smax(Y, 0), 2^n))))) pattern.
define <16 x i8> @sminsmax_range_unsigned_i16_to_i8(<8 x i8> %x, <8 x i16> %y) {
-; CHECK-LABEL: sminsmax_range_unsigned_i16_to_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtun2 v0.16b, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_unsigned_i16_to_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtun2 v0.16b, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_unsigned_i16_to_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v3.2d, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smax v1.8h, v1.8h, v2.8h
+; CHECK-GI-NEXT: smin v1.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: xtn2 v0.16b, v1.8h
+; CHECK-GI-NEXT: ret
entry:
%min = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %y, <8 x i16> zeroinitializer)
%max = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %min, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
@@ -395,11 +670,21 @@ entry:
}
define <8 x i16> @sminsmax_range_unsigned_i32_to_i16(<4 x i16> %x, <4 x i32> %y) {
-; CHECK-LABEL: sminsmax_range_unsigned_i32_to_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtun2 v0.8h, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_unsigned_i32_to_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtun2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_unsigned_i32_to_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v3.2d, #0x00ffff0000ffff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-GI-NEXT: ret
entry:
%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> zeroinitializer)
%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %smax, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -409,11 +694,22 @@ entry:
}
define <4 x i32> @sminsmax_range_unsigned_i64_to_i32(<2 x i32> %x, <2 x i64> %y) {
-; CHECK-LABEL: sminsmax_range_unsigned_i64_to_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqxtun2 v0.4s, v1.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_unsigned_i64_to_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqxtun2 v0.4s, v1.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_unsigned_i64_to_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, #0
+; CHECK-GI-NEXT: movi v3.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: cmgt v2.2d, v3.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: xtn2 v0.4s, v1.2d
+; CHECK-GI-NEXT: ret
entry:
%smax = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> zeroinitializer)
%smin = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %smax, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -425,16 +721,31 @@ entry:
; Type support varification - not supported with saturated value
; i64 -> i16
define <4 x i16> @sminsmax_range_unsigned_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
-; CHECK-LABEL: sminsmax_range_unsigned_i64_to_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v2.2d, v1.2d, #0
-; CHECK-NEXT: movi v3.2d, #0x0000000000ffff
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: cmgt v2.2d, v3.2d, v1.2d
-; CHECK-NEXT: bif v1.16b, v3.16b, v2.16b
-; CHECK-NEXT: xtn v1.2s, v1.2d
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_unsigned_i64_to_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: cmgt v2.2d, v1.2d, #0
+; CHECK-SD-NEXT: movi v3.2d, #0x0000000000ffff
+; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: cmgt v2.2d, v3.2d, v1.2d
+; CHECK-SD-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: xtn v1.2s, v1.2d
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_unsigned_i64_to_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, #0
+; CHECK-GI-NEXT: movi v3.2d, #0x0000000000ffff
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: cmgt v2.2d, v3.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: xtn v1.2s, v1.2d
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> zeroinitializer)
%smin = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %smax, <2 x i64> <i64 65535, i64 65535>)
@@ -444,19 +755,37 @@ entry:
}
define <4 x i16> @sminsmax_range_signed_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
-; CHECK-LABEL: sminsmax_range_signed_i64_to_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, #-32768 // =0xffffffffffff8000
-; CHECK-NEXT: dup v2.2d, x8
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-NEXT: dup v2.2d, x8
-; CHECK-NEXT: cmgt v3.2d, v2.2d, v1.2d
-; CHECK-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-NEXT: xtn v1.2s, v1.2d
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_signed_i64_to_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x8, #-32768 // =0xffffffffffff8000
+; CHECK-SD-NEXT: dup v2.2d, x8
+; CHECK-SD-NEXT: mov w8, #32767 // =0x7fff
+; CHECK-SD-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-SD-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: dup v2.2d, x8
+; CHECK-SD-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-SD-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: xtn v1.2s, v1.2d
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_signed_i64_to_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI31_1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI31_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI31_0
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI31_0]
+; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: xtn v1.2s, v1.2d
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> <i64 -32768, i64 -32768>)
%smin = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %smax, <2 x i64> <i64 32767, i64 32767>)
@@ -466,14 +795,27 @@ entry:
}
define <4 x i16> @umin_range_unsigned_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
-; CHECK-LABEL: umin_range_unsigned_i64_to_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.2d, #0x0000000000ffff
-; CHECK-NEXT: cmhi v3.2d, v2.2d, v1.2d
-; CHECK-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-NEXT: xtn v1.2s, v1.2d
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: umin_range_unsigned_i64_to_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2d, #0x0000000000ffff
+; CHECK-SD-NEXT: cmhi v3.2d, v2.2d, v1.2d
+; CHECK-SD-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: xtn v1.2s, v1.2d
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: umin_range_unsigned_i64_to_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0x0000000000ffff
+; CHECK-GI-NEXT: cmhi v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: xtn v1.2s, v1.2d
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%umin = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %y, <2 x i64> <i64 65535, i64 65535>)
%trunc = trunc <2 x i64> %umin to <2 x i16>
@@ -483,15 +825,29 @@ entry:
; i32 -> i8
define <8 x i8> @sminsmax_range_unsigned_i64_to_i8(<4 x i8> %x, <4 x i32> %y) {
-; CHECK-LABEL: sminsmax_range_unsigned_i64_to_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff
-; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: xtn v1.4h, v1.4s
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_unsigned_i64_to_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2d, #0000000000000000
+; CHECK-SD-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-SD-NEXT: smin v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: xtn v1.4h, v1.4s
+; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_unsigned_i64_to_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v3.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: xtn v1.4h, v1.4s
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> zeroinitializer)
%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %smax, <4 x i32> <i32 255, i32 255, i32 255, i32 255>)
@@ -501,15 +857,29 @@ entry:
}
define <8 x i8> @sminsmax_range_signed_i32_to_i8(<4 x i8> %x, <4 x i32> %y) {
-; CHECK-LABEL: sminsmax_range_signed_i32_to_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mvni v2.4s, #127
-; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: movi v2.4s, #127
-; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: xtn v1.4h, v1.4s
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_signed_i32_to_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mvni v2.4s, #127
+; CHECK-SD-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: movi v2.4s, #127
+; CHECK-SD-NEXT: smin v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: xtn v1.4h, v1.4s
+; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_signed_i32_to_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mvni v2.4s, #127
+; CHECK-GI-NEXT: movi v3.4s, #127
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: xtn v1.4h, v1.4s
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> <i32 -128, i32 -128, i32 -128, i32 -128>)
%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %smax, <4 x i32> <i32 127, i32 127, i32 127, i32 127>)
@@ -519,16 +889,30 @@ entry:
}
define <8 x i8> @umin_range_unsigned_i32_to_i8(<4 x i8> %x, <4 x i32> %y) {
-; CHECK-LABEL: umin_range_unsigned_i32_to_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff
-; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: xtn v1.4h, v1.4s
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: umin_range_unsigned_i32_to_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-SD-NEXT: umin v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: xtn v1.4h, v1.4s
+; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: umin_range_unsigned_i32_to_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: umin v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: xtn v1.4h, v1.4s
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%umin = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %y, <4 x i32> <i32 255, i32 255, i32 255, i32 255>)
%trunc = trunc <4 x i32> %umin to <4 x i8>
%shuffle = shufflevector <4 x i8> %x, <4 x i8> %trunc, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %shuffle
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
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