[llvm] [RISCV][GlobalISel] Legalize and select G_ATOMICRMW_ADD instruction (PR #153791)

[Kane Wang via llvm-commits]

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@@ -1415,6 +1418,72 @@ void RISCVInstructionSelector::emitFence(AtomicOrdering FenceOrdering,
   MIB.buildInstr(RISCV::FENCE, {}, {}).addImm(Pred).addImm(Succ);
 }
 
+bool RISCVInstructionSelector::selectAtomicRMWAdd(MachineInstr &MI,
+                                                  MachineIRBuilder &MIB) const {
+  MachineBasicBlock &MBB = *MI.getParent();
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ReVe1uv wrote:

I tried adding
`def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add>;`
in llvm/lib/Target/RISCV/RISCVInstrGISel.td. With this change, on riscv64a, G_ATOMICRMW_ADD instructions with 64-bit data width correctly select AMOADD_D. However, G_ATOMICRMW_ADD instructions with 32-bit data width **do not** select AMOADD_D on riscv64a (selection works correctly on riscv32a).

https://github.com/llvm/llvm-project/pull/153791