[llvm] [AMDGPU] Add support for store to constant address space (PR #153835)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o - | FileCheck %s
+
+define amdgpu_kernel void @store_as4(ptr addrspace(4) %out, i32 %a, i32 %b) {
+; CHECK-LABEL: store_as4:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
+; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_add_i32 s2, s2, s3
+; CHECK-NEXT:    v_mov_b32_e32 v1, s2
+; CHECK-NEXT:    global_store_dword v0, v1, s[0:1]
+; CHECK-NEXT:    s_endpgm
+  %r = add i32 %a, %b
+  store i32 %r, ptr addrspace(4) %out
+  ret void
+}
+
+define amdgpu_kernel void @memset_as4(ptr addrspace(4) %dst) {
+; CHECK-LABEL: memset_as4:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x0
+; CHECK-NEXT:    s_mov_b32 s0, 0
+; CHECK-NEXT:    s_mov_b32 s1, s0
+; CHECK-NEXT:    s_mov_b32 s2, s0
+; CHECK-NEXT:    s_mov_b32 s3, s0
+; CHECK-NEXT:    v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:240
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:224
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:208
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:192
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:176
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:160
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:144
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:128
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:112
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:96
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:80
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:64
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:48
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:32
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5] offset:16
+; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5]
+; CHECK-NEXT:    s_endpgm
+  call void @llvm.memset.p4.i64(ptr addrspace(4) %dst, i8 0, i64 256, i1 false)
+  ret void
+}
+
+define amdgpu_kernel void @memcpy_to_as4(ptr addrspace(4) %dst, ptr %src) {
+; CHECK-LABEL: memcpy_to_as4:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
+; CHECK-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
+; CHECK-NEXT:    flat_load_dwordx4 v[4:7], v[0:1] offset:112
+; CHECK-NEXT:    flat_load_dwordx4 v[8:11], v[0:1] offset:96
+; CHECK-NEXT:    flat_load_dwordx4 v[12:15], v[0:1] offset:80
+; CHECK-NEXT:    flat_load_dwordx4 v[16:19], v[0:1] offset:64
+; CHECK-NEXT:    flat_load_dwordx4 v[20:23], v[0:1] offset:48
+; CHECK-NEXT:    flat_load_dwordx4 v[24:27], v[0:1] offset:32
+; CHECK-NEXT:    flat_load_dwordx4 v[28:31], v[0:1] offset:16
+; CHECK-NEXT:    flat_load_dwordx4 v[32:35], v[0:1]
+; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    global_store_dwordx4 v2, v[4:7], s[0:1] offset:112
+; CHECK-NEXT:    global_store_dwordx4 v2, v[8:11], s[0:1] offset:96
+; CHECK-NEXT:    global_store_dwordx4 v2, v[12:15], s[0:1] offset:80
+; CHECK-NEXT:    global_store_dwordx4 v2, v[16:19], s[0:1] offset:64
+; CHECK-NEXT:    global_store_dwordx4 v2, v[20:23], s[0:1] offset:48
+; CHECK-NEXT:    global_store_dwordx4 v2, v[24:27], s[0:1] offset:32
+; CHECK-NEXT:    global_store_dwordx4 v2, v[28:31], s[0:1] offset:16
+; CHECK-NEXT:    global_store_dwordx4 v2, v[32:35], s[0:1]
+; CHECK-NEXT:    flat_load_dwordx4 v[4:7], v[0:1] offset:240
+; CHECK-NEXT:    flat_load_dwordx4 v[8:11], v[0:1] offset:224
+; CHECK-NEXT:    flat_load_dwordx4 v[12:15], v[0:1] offset:208
+; CHECK-NEXT:    flat_load_dwordx4 v[16:19], v[0:1] offset:192
+; CHECK-NEXT:    flat_load_dwordx4 v[20:23], v[0:1] offset:176
+; CHECK-NEXT:    flat_load_dwordx4 v[24:27], v[0:1] offset:160
+; CHECK-NEXT:    flat_load_dwordx4 v[28:31], v[0:1] offset:144
+; CHECK-NEXT:    flat_load_dwordx4 v[32:35], v[0:1] offset:128
+; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    global_store_dwordx4 v2, v[4:7], s[0:1] offset:240
+; CHECK-NEXT:    global_store_dwordx4 v2, v[8:11], s[0:1] offset:224
+; CHECK-NEXT:    global_store_dwordx4 v2, v[12:15], s[0:1] offset:208
+; CHECK-NEXT:    global_store_dwordx4 v2, v[16:19], s[0:1] offset:192
+; CHECK-NEXT:    global_store_dwordx4 v2, v[20:23], s[0:1] offset:176
+; CHECK-NEXT:    global_store_dwordx4 v2, v[24:27], s[0:1] offset:160
+; CHECK-NEXT:    global_store_dwordx4 v2, v[28:31], s[0:1] offset:144
+; CHECK-NEXT:    global_store_dwordx4 v2, v[32:35], s[0:1] offset:128
+; CHECK-NEXT:    s_endpgm
+  call void @llvm.memcpy.p4.p0.i32(ptr addrspace(4) %dst, ptr %src, i32 256, i1 false)
+  ret void
+}
+
----------------
arsenm wrote:

Memmove 

https://github.com/llvm/llvm-project/pull/153835