[llvm] [RISCV] Unaligned vec mem => prefer alt opc vec (PR #154153)

[Pengcheng Wang via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -mtriple=riscv64 -mattr=+v,+unaligned-vector-mem \
+; RUN: -passes=slp-vectorizer -S \
+; RUN: < %s | FileCheck %s --check-prefixes=UNALIGNED_VEC_MEM
+
+; RUN: opt -mtriple=riscv64 -mattr=+v \
+; RUN: -passes=slp-vectorizer -S \
+; RUN: < %s | FileCheck %s --check-prefixes=NO_UNALIGNED_VEC_MEM
+
+define void @alternate_opcodes(ptr %pl, ptr %ps, i8 %x) {
+; UNALIGNED_VEC_MEM-LABEL: define void @alternate_opcodes(
+; UNALIGNED_VEC_MEM-SAME: ptr [[PL:%.*]], ptr [[PS:%.*]], i8 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; UNALIGNED_VEC_MEM-NEXT:    [[GEP_L0:%.*]] = getelementptr inbounds i8, ptr [[PL]], i64 0
+; UNALIGNED_VEC_MEM-NEXT:    [[GEP_S0:%.*]] = getelementptr inbounds i8, ptr [[PS]], i64 0
+; UNALIGNED_VEC_MEM-NEXT:    [[TMP1:%.*]] = call <8 x i8> @llvm.experimental.vp.strided.load.v8i8.p0.i64(ptr align 1 [[GEP_L0]], i64 20, <8 x i1> splat (i1 true), i32 8)
+; UNALIGNED_VEC_MEM-NEXT:    [[TMP6:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i32 0
+; UNALIGNED_VEC_MEM-NEXT:    [[TMP3:%.*]] = shufflevector <8 x i8> [[TMP6]], <8 x i8> poison, <8 x i32> zeroinitializer
+; UNALIGNED_VEC_MEM-NEXT:    [[TMP4:%.*]] = add <8 x i8> [[TMP1]], [[TMP3]]
+; UNALIGNED_VEC_MEM-NEXT:    [[TMP5:%.*]] = sub <8 x i8> [[TMP1]], [[TMP3]]
+; UNALIGNED_VEC_MEM-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; UNALIGNED_VEC_MEM-NEXT:    store <8 x i8> [[TMP2]], ptr [[GEP_S0]], align 1
+; UNALIGNED_VEC_MEM-NEXT:    ret void
+;
+; NO_UNALIGNED_VEC_MEM-LABEL: define void @alternate_opcodes(
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wangpc-pp wrote:

What is the difference? I may miss it…

https://github.com/llvm/llvm-project/pull/154153