[llvm] [RISCV] Add initial assembler/MC layer support for big-endian (PR #146534)

[Fangrui Song via llvm-commits]

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@@ -869,6 +871,41 @@ bool RISCVAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
   return false;
 }
 
+// Data should be swapped for big endian cores.
+static bool isDataFixup(unsigned Kind) {
+  switch (Kind) {
+  default:
+    llvm_unreachable("Unknown fixup kind!");
+
+  case FK_Data_1:
+  case FK_Data_2:
+  case FK_Data_4:
+  case FK_Data_8:
+    return true;
+
+  case RISCV::fixup_riscv_hi20:
----------------
MaskRay wrote:

delete all `fixup_riscv_*` cases - these are all instruction kinds.
If we ever have fixups for data relocations, we could add them like FK_Data_8 in the future.

https://github.com/llvm/llvm-project/pull/146534