[llvm] [RISCV] Fold (sext_inreg (setcc), i1) -> (sub 0, (setcc). (PR #154206)

[Jessica Clarke via llvm-commits]

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@@ -394,8 +394,9 @@ define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
 define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
 ; CHECK-LABEL: sexti1_i32_setcc_3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slt a0, a0, a1
-; CHECK-NEXT:    nds.bfos a0, a0, 0, 0
+; CHECK-NEXT:    slt a1, a0, a1
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    sub a0, a0, a1
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jrtc27 wrote:

Particularly weird when the rv64 one doesn't. Been that way since both were added in c78e6bbd830a4633fa7c80aebb9680b6acf913c6.

https://github.com/llvm/llvm-project/pull/154206