[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sam Tebbs via llvm-commits]

================
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
----------------
SamTebbs33 wrote:

I could be missing something but if we merge them, then the sve-less run line will fail since it can't handle the scalable vector test.

https://github.com/llvm/llvm-project/pull/117007