[llvm] [AArch64][llvm] Disassemble instructions in `SYS` alias encoding space more correctly (PR #153905)

[via llvm-commits]

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@@ -1017,13 +1017,22 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   else
     return false;
 
+  StringRef Reg = getRegisterName(MI->getOperand(4).getReg());
+  bool NotXZR = Reg != "xzr";
+
+  // If a mandatory is not specified in the TableGen
+  // (i.e. no register operand should be present), and the register value
+  // is not xzr/x31, then disassemble to a SYS alias instead.
+  if (NotXZR && !NeedsReg)
+    return false;
+
   std::string Str = Ins + Name;
   llvm::transform(Str, Str.begin(), ::tolower);
 
   O << '\t' << Str;
+
   if (NeedsReg) {
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CarolineConcatto wrote:

nit: If this is only 1 line we can remove the brackets, right?

https://github.com/llvm/llvm-project/pull/153905