[llvm] [CodeGen] Add laneBitmask as new MachineOperand type, utilised by newly defined COPY_LANEMASK instruction (PR #151944)

[Diana Picus via llvm-commits]

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@@ -807,6 +807,19 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
 
    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
 
+Lanemask Operands
+^^^^^^^^^^^^^^^^^^
+
+A Lanemask operand is 64-bit unsigned value that holds the lane information 
+corrseponding to the source register operand in the instruction.
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rovka wrote:

Does this mean that lanemask operands can only be used on instructions with a single source register operand? Or would it be possible in the future to have `$vgpr0 = SOME_OTHER_OP $vgpr1, $vgpr2, lanemask(0x42)`, in which case it applies to all register operands? Can an instruction have more than one lanemask operand? Please clarify this in the docs (and add more verifier checks if relevant)

I think you need to abstract this whole concept a bit more, since this document is target-independent, and many targets don't have hidden lanes like AMDGPU does. Are you planning to use these in any target-independent passes? If not, then we might get away with smth hand-wavy like "the interpretation of lanemasks is up to each target", but otherwise I think you'll need to be more specific about how this behaves.

https://github.com/llvm/llvm-project/pull/151944