[llvm] [AMDGPU] Examine instructions in pending queues during scheduling (PR #147653)

[Jay Foad via llvm-commits]

jayfoad wrote:

> The scheduler has two hardware resource modeling modes: an in-order mode where instructions must be ready to issue before scheduling, and out-of-order models where instructions are always visible to heuristics. Special handling exists for unbuffered processor resources in out-of-order models. These resources can cause pipeline stalls when used back-to-back, so they're typically avoided. However, for AMDGPU targets, managing register pressure and reducing spilling is critical enough to justify exceptions to this approach.

To clarify: the case you want to improve is the handling of unbuffered resources (BufferSize == 0) in an out-of-order model (MicroOpBufferSize >= 1), right? What exactly is the "special handling" for this case that you mention?

My gut feeling is that "examining instructions in the pending queue when scheduling" destroys the distinction between the available and pending queues. Is there an alternative approach that puts the instructions in the available queue instead? Or can you simply use a buffered resource instead of an unbuffered one - or does that change the behavior in other ways?

https://github.com/llvm/llvm-project/pull/147653