[llvm] [RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (PR #154023)

[Sam Elliott via llvm-commits]

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@@ -764,14 +757,14 @@ bool RISCVDAGToDAGISel::tryBitfieldInsertOpFromOrAndImm(SDNode *Node) {
   // QC_INSB(I) dst, src, #width, #shamt.
   MVT VT = Node->getSimpleValueType(0);
   unsigned BitWidth = VT.getSizeInBits();
-  const unsigned ShAmt = llvm::countr_one(NotKnownZero);
-  const unsigned Width = BitWidth - APInt(BitWidth, NotKnownZero).popcount();
+  const unsigned ShAmt = llvm::countr_one(NotKnownZero.getZExtValue());
+  const unsigned Width = BitWidth - NotKnownZero.popcount();
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lenary wrote:

There's a version of `isShiftedMask` that will give you both of these as out-parameters.

https://github.com/llvm/llvm-project/pull/154023