[llvm] [LoongArch] Use section-relaxable check instead of relax feature from STI (PR #153792)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 17 19:59:31 PDT 2025
https://github.com/zhaoqi5 updated https://github.com/llvm/llvm-project/pull/153792
>From 30d6e76ba992a0b56242aff101c778ce0de50b1b Mon Sep 17 00:00:00 2001
From: Qi Zhao <zhaoqi01 at loongson.cn>
Date: Mon, 18 Aug 2025 10:21:59 +0800
Subject: [PATCH 1/3] [LoongArch][NFC] Add tests for fixing addsub relocs when
enabling relax
---
.../LoongArch/fix-addsub-relocs-with-relax.ll | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll
diff --git a/llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll b/llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll
new file mode 100644
index 0000000000000..b09aa1e49255d
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll
@@ -0,0 +1,83 @@
+; RUN: llc --filetype=obj --mtriple=loongarch64 %s -o %t.o
+; RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=CHECK,RELOC %s
+
+; RUN: llc --filetype=obj --mtriple=loongarch64 --mattr=+relax %s -o %t.r
+; RUN: llvm-readobj -r %t.r | FileCheck --check-prefixes=CHECK,RELAX %s
+
+; CHECK: Relocations [
+; CHECK-NEXT: Section ({{.*}}) .rela.text {
+; CHECK-NEXT: 0x0 R_LARCH_ALIGN - 0x1C
+; CHECK-NEXT: 0x30 R_LARCH_PCALA_HI20 sym 0x0
+; CHECK-NEXT: 0x30 R_LARCH_RELAX - 0x0
+; CHECK-NEXT: 0x34 R_LARCH_PCALA_LO12 sym 0x0
+; CHECK-NEXT: 0x34 R_LARCH_RELAX - 0x0
+; CHECK-NEXT: }
+; CHECK-NEXT: Section ({{.*}}) .rela.debug_info {
+; CHECK-NEXT: 0x8 R_LARCH_32 .debug_abbrev 0x0
+; RELOC-NEXT: 0x11 R_LARCH_32 .debug_str_offsets 0x8
+; RELAX-NEXT: 0x11 R_LARCH_32 .L0 0x0
+; RELOC-NEXT: 0x15 R_LARCH_32 .debug_line 0x0
+; RELAX-NEXT: 0x15 R_LARCH_32 .Lline_table_start0 0x0
+; RELAX-NEXT: 0x1B R_LARCH_ADD32 .L0 0x0
+; RELAX-NEXT: 0x1B R_LARCH_SUB32 .L0 0x0
+; RELOC-NEXT: 0x1F R_LARCH_32 .debug_addr 0x8
+; RELAX-NEXT: 0x1F R_LARCH_32 .L0 0x0
+; RELAX-NEXT: 0x25 R_LARCH_ADD32 .L0 0x0
+; RELAX-NEXT: 0x25 R_LARCH_SUB32 .L0 0x0
+; CHECK-NEXT: }
+; CHECK: Section ({{.*}}) .rela.debug_frame {
+; RELOC-NEXT: 0x1C R_LARCH_32 .debug_frame 0x0
+; RELAX-NEXT: 0x1C R_LARCH_32 .L0 0x0
+; RELOC-NEXT: 0x20 R_LARCH_64 .text 0x1C
+; RELAX-NEXT: 0x20 R_LARCH_64 .L0 0x0
+; RELAX-NEXT: 0x28 R_LARCH_ADD64 .L0 0x0
+; RELAX-NEXT: 0x28 R_LARCH_SUB64 .L0 0x0
+; RELOC-NEXT: 0x3F R_LARCH_ADD6 .text 0x3C
+; RELOC-NEXT: 0x3F R_LARCH_SUB6 .text 0x2C
+; RELAX-NEXT: 0x3F R_LARCH_ADD6 .L0 0x0
+; RELAX-NEXT: 0x3F R_LARCH_SUB6 .L0 0x0
+; CHECK-NEXT: }
+; CHECK-NEXT: Section ({{.*}}) .rela.debug_line {
+; CHECK-NEXT: 0x22 R_LARCH_32 .debug_line_str 0x0
+; CHECK-NEXT: 0x31 R_LARCH_32 .debug_line_str 0x2
+; CHECK-NEXT: 0x46 R_LARCH_32 .debug_line_str 0x9
+; RELOC-NEXT: 0x4F R_LARCH_64 .text 0x1C
+; RELAX-NEXT: 0x4F R_LARCH_64 .L0 0x0
+; RELAX-NEXT: 0x5F R_LARCH_ADD16 .L0 0x0
+; RELAX-NEXT: 0x5F R_LARCH_SUB16 .L0 0x0
+; CHECK-NEXT: }
+; CHECK-NEXT: ]
+
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "loongarch64"
+
+; Function Attrs: noinline nounwind optnone
+define dso_local signext i32 @foo() #0 !dbg !8 {
+ call void asm sideeffect ".cfi_remember_state\0A\09.cfi_adjust_cfa_offset 16\0A\09nop\0A\09la.pcrel $$t0, sym\0A\09nop\0A\09.cfi_restore_state\0A\09", ""() #1, !dbg !12, !srcloc !13
+ ret i32 0, !dbg !14
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="loongarch64" "target-features"="+64bit,+d,+f,+ual,+relax" }
+attributes #1 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3, !4, !5, !6}
+!llvm.ident = !{!7}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "test.c", directory: ".", checksumkind: CSK_MD5, checksum: "f44d6d71bc4da58b4abe338ca507c007", source: "int foo()\0A{\0A asm volatile(\0A \22.cfi_remember_state\\n\\t\22\0A \22.cfi_adjust_cfa_offset 16\\n\\t\22\0A \22nop\\n\\t\22\0A \22la.pcrel $t0, sym\\n\\t\22\0A \22nop\\n\\t\22\0A \22.cfi_restore_state\\n\\t\22);\0A return 0;\0A}\0A")
+!2 = !{i32 7, !"Dwarf Version", i32 5}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"wchar_size", i32 4}
+!5 = !{i32 7, !"direct-access-external-data", i32 0}
+!6 = !{i32 7, !"frame-pointer", i32 2}
+!7 = !{!"clang"}
+!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !9, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0)
+!9 = !DISubroutineType(types: !10)
+!10 = !{!11}
+!11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!12 = !DILocation(line: 3, column: 3, scope: !8)
+!13 = !{i64 34, i64 56, i64 92, i64 106, i64 134, i64 148, i64 177}
+!14 = !DILocation(line: 10, column: 3, scope: !8)
>From 1a8b15a2c87e9673269a37959a8f3d1eab6512b1 Mon Sep 17 00:00:00 2001
From: Qi Zhao <zhaoqi01 at loongson.cn>
Date: Fri, 15 Aug 2025 19:25:59 +0800
Subject: [PATCH 2/3] [LoongArch] Use section-relaxable check instead of relax
feature from STI
In some cases, such as using lto or llc, relax feature is not
available from this SubtargetInfo (LoongArchAsmBackend is instantiated
too early), causing loss of relocations.
This commit modifiy the condition to check whether the section
which contains the two symbols is relaxable. If not relaxable,
no need to record relocations.
---
.../lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
index ca5d27d54bb81..34a5d802daed6 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
@@ -448,10 +448,10 @@ bool LoongArchAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
isPCRelFixupResolved(Target.getSubSym(), F))
return Fallback();
- // In SecA == SecB case. If the linker relaxation is disabled, the
+ // In SecA == SecB case. If the section is not linker-relaxable, the
// FixedValue has already been calculated out in evaluateFixup,
// return true and avoid record relocations.
- if (&SecA == &SecB && !STI.hasFeature(LoongArch::FeatureRelax))
+ if (&SecA == &SecB && !SecA.isLinkerRelaxable())
return true;
}
>From c0ecb4849c2f147c3d01741cbee95596857400d9 Mon Sep 17 00:00:00 2001
From: Qi Zhao <zhaoqi01 at loongson.cn>
Date: Mon, 18 Aug 2025 10:56:00 +0800
Subject: [PATCH 3/3] update tests
---
.../CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll b/llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll
index b09aa1e49255d..24aa7a03cbc14 100644
--- a/llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll
+++ b/llvm/test/CodeGen/LoongArch/fix-addsub-relocs-with-relax.ll
@@ -18,10 +18,14 @@
; RELAX-NEXT: 0x11 R_LARCH_32 .L0 0x0
; RELOC-NEXT: 0x15 R_LARCH_32 .debug_line 0x0
; RELAX-NEXT: 0x15 R_LARCH_32 .Lline_table_start0 0x0
+; RELOC-NEXT: 0x1B R_LARCH_ADD32 .text 0x50
+; RELOC-NEXT: 0x1B R_LARCH_SUB32 .text 0x1C
; RELAX-NEXT: 0x1B R_LARCH_ADD32 .L0 0x0
; RELAX-NEXT: 0x1B R_LARCH_SUB32 .L0 0x0
; RELOC-NEXT: 0x1F R_LARCH_32 .debug_addr 0x8
; RELAX-NEXT: 0x1F R_LARCH_32 .L0 0x0
+; RELOC-NEXT: 0x25 R_LARCH_ADD32 .text 0x50
+; RELOC-NEXT: 0x25 R_LARCH_SUB32 .text 0x1C
; RELAX-NEXT: 0x25 R_LARCH_ADD32 .L0 0x0
; RELAX-NEXT: 0x25 R_LARCH_SUB32 .L0 0x0
; CHECK-NEXT: }
@@ -30,6 +34,8 @@
; RELAX-NEXT: 0x1C R_LARCH_32 .L0 0x0
; RELOC-NEXT: 0x20 R_LARCH_64 .text 0x1C
; RELAX-NEXT: 0x20 R_LARCH_64 .L0 0x0
+; RELOC-NEXT: 0x28 R_LARCH_ADD64 .text 0x50
+; RELOC-NEXT: 0x28 R_LARCH_SUB64 .text 0x1C
; RELAX-NEXT: 0x28 R_LARCH_ADD64 .L0 0x0
; RELAX-NEXT: 0x28 R_LARCH_SUB64 .L0 0x0
; RELOC-NEXT: 0x3F R_LARCH_ADD6 .text 0x3C
@@ -43,6 +49,8 @@
; CHECK-NEXT: 0x46 R_LARCH_32 .debug_line_str 0x9
; RELOC-NEXT: 0x4F R_LARCH_64 .text 0x1C
; RELAX-NEXT: 0x4F R_LARCH_64 .L0 0x0
+; RELOC-NEXT: 0x5F R_LARCH_ADD16 .text 0x3C
+; RELOC-NEXT: 0x5F R_LARCH_SUB16 .text 0x2C
; RELAX-NEXT: 0x5F R_LARCH_ADD16 .L0 0x0
; RELAX-NEXT: 0x5F R_LARCH_SUB16 .L0 0x0
; CHECK-NEXT: }
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