[llvm] [LegalizeTypes][VP] Teach isVPBinaryOp to recognize vp.sadd/saddu/ssub/ssubu.sat (PR #154047)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 17 19:45:45 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-ir
@llvm/pr-subscribers-backend-risc-v
Author: Jim Lin (tclin914)
<details>
<summary>Changes</summary>
Those vp intrinsics also are vp binary operations. Similar to https://reviews.llvm.org/D135753.
---
Full diff: https://github.com/llvm/llvm-project/pull/154047.diff
5 Files Affected:
- (modified) llvm/include/llvm/IR/VPIntrinsics.def (+4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll (-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll (-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll (-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll (-10)
``````````diff
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 4a71097226f18..cd7343ff8df56 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -278,24 +278,28 @@ END_REGISTER_VP(vp_fshr, VP_FSHR)
// llvm.vp.sadd.sat(x,y,mask,vlen)
BEGIN_REGISTER_VP(vp_sadd_sat, 2, 3, VP_SADDSAT, -1)
+VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_INTRINSIC(sadd_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
END_REGISTER_VP(vp_sadd_sat, VP_SADDSAT)
// llvm.vp.uadd.sat(x,y,mask,vlen)
BEGIN_REGISTER_VP(vp_uadd_sat, 2, 3, VP_UADDSAT, -1)
+VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_INTRINSIC(uadd_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
END_REGISTER_VP(vp_uadd_sat, VP_UADDSAT)
// llvm.vp.ssub.sat(x,y,mask,vlen)
BEGIN_REGISTER_VP(vp_ssub_sat, 2, 3, VP_SSUBSAT, -1)
+VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_INTRINSIC(ssub_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(SSUBSAT)
END_REGISTER_VP(vp_ssub_sat, VP_SSUBSAT)
// llvm.vp.usub.sat(x,y,mask,vlen)
BEGIN_REGISTER_VP(vp_usub_sat, 2, 3, VP_USUBSAT, -1)
+VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_INTRINSIC(usub_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT)
END_REGISTER_VP(vp_usub_sat, VP_USUBSAT)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
index a04e31a19a4f1..546353dada758 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
@@ -439,14 +439,9 @@ define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsadd_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -1418,13 +1413,8 @@ define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsadd_vx_v32i64_evl12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
index 5556b11e9a90c..1caadb1906aea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
@@ -435,14 +435,9 @@ define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsaddu_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -1414,13 +1409,8 @@ define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsaddu_vx_v32i64_evl12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
index c28317bf14269..62cbba7769640 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
@@ -454,15 +454,10 @@ define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssub_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -1460,14 +1455,9 @@ define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssub_vx_v32i64_evl12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
index cbfe1292877ee..247501ccbb161 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
@@ -449,15 +449,10 @@ define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssubu_vi_v258i8_evl128:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -1455,14 +1450,9 @@ define <32 x i64> @vssubu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssubu_vx_v32i64_evl12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
``````````
</details>
https://github.com/llvm/llvm-project/pull/154047
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