[llvm] [DAG] fix wrong type check in DAGCombiner::visitSRA (PR #153762)

[via llvm-commits]

akiva-pripas wrote:

I can provide the selectionDAG before and after the optimization takes place when it shouldn't:

Vector/type-legalized selection DAG: %bb.11 'vector_aint_shift_aint:vector.body27'
SelectionDAG has 44 nodes:
  t0: ch,glue = EntryToken
  t2: i32,ch = CopyFromReg t0, Register:i32 %17
  t13: i32,ch = CopyFromReg t0, Register:i32 %16
  t57: v8i64 = BUILD_VECTOR Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>
  t43: v8i64,ch = load<(load (s512) from %ir.lsr.iv45, align 4, !tbaa !33)> t0, t2, undef:i32
    t23: i32,ch = CopyFromReg t0, Register:i32 %15
  t25: i32 = add nsw t23, Constant:i32<-16>
    t45: i32 = add nuw t2, Constant:i32<64>
  t46: v8i64,ch = load<(load (s512) from %ir.lsr.iv45 + 64, align 4, !tbaa !33)> t0, t45, undef:i32
  t47: ch = TokenFactor t43:1, t46:1
  t69: v8i64 = BUILD_VECTOR Constant:i64<63>, Constant:i64<63>, Constant:i64<63>, Constant:i64<63>, Constant:i64<63>, Constant:i64<63>, Constant:i64<63>, Constant:i64<63>
          t16: i32 = add t2, Constant:i32<128>
        t18: ch = CopyToReg t0, Register:i32 %18, t16
          t19: i32 = add t13, Constant:i32<128>
        t21: ch = CopyToReg t0, Register:i32 %19, t19
        t27: ch = CopyToReg t0, Register:i32 %20, t25
              t63: v8i64 = srl t43, t57
            t70: v8i64 = shl t63, t69
          t71: v8i64 = sra t70, t69
        t52: ch = store<(store (s512) into %ir.lsr.iv47, align 4, !tbaa !33)> t47, t71, t13, undef:i32
              t58: v8i64 = srl t46, t57
            t72: v8i64 = shl t58, t69
          t73: v8i64 = sra t72, t69
          t53: i32 = add nuw t13, Constant:i32<64>
        t54: ch = store<(store (s512) into %ir.lsr.iv47 + 64, align 4, !tbaa !33)> t47, t73, t53, undef:i32
      t67: ch = TokenFactor t18, t21, t27, t52, t54
    t40: ch = br_cc t67, setne:ch, t25, Constant:i32<0>, BasicBlock:ch<vector.body27 0x2a12f621658>
  t36: ch = br t40, BasicBlock:ch<middle.block21 0x2a12f621910>



Optimized vector-legalized selection DAG: %bb.11 'vector_aint_shift_aint:vector.body27'
SelectionDAG has 42 nodes:
  t0: ch,glue = EntryToken
  t2: i32,ch = CopyFromReg t0, Register:i32 %17
  t13: i32,ch = CopyFromReg t0, Register:i32 %16
  t57: v8i64 = BUILD_VECTOR Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>
  t43: v8i64,ch = load<(load (s512) from %ir.lsr.iv45, align 4, !tbaa !33)> t0, t2, undef:i32
    t23: i32,ch = CopyFromReg t0, Register:i32 %15
  t25: i32 = add nsw t23, Constant:i32<-16>
    t45: i32 = add nuw t2, Constant:i32<64>
  t46: v8i64,ch = load<(load (s512) from %ir.lsr.iv45 + 64, align 4, !tbaa !33)> t0, t45, undef:i32
  t47: ch = TokenFactor t43:1, t46:1
          t16: i32 = add t2, Constant:i32<128>
        t18: ch = CopyToReg t0, Register:i32 %18, t16
          t19: i32 = add t13, Constant:i32<128>
        t21: ch = CopyToReg t0, Register:i32 %19, t19
        t27: ch = CopyToReg t0, Register:i32 %20, t25
              t83: v8i64 = srl t43, t57
            t84: v8i1 = truncate t83
          t85: v8i64 = sign_extend t84
        t52: ch = store<(store (s512) into %ir.lsr.iv47, align 4, !tbaa !33)> t47, t85, t13, undef:i32
              t77: v8i64 = srl t46, t57
            t78: v8i1 = truncate t77
          t79: v8i64 = sign_extend t78
          t53: i32 = add nuw t13, Constant:i32<64>
        t54: ch = store<(store (s512) into %ir.lsr.iv47 + 64, align 4, !tbaa !33)> t47, t79, t53, undef:i32
      t67: ch = TokenFactor t18, t21, t27, t52, t54
    t40: ch = br_cc t67, setne:ch, t25, Constant:i32<0>, BasicBlock:ch<vector.body27 0x2a12f621658>
  t36: ch = br t40, BasicBlock:ch<middle.block21 0x2a12f621910>

https://github.com/llvm/llvm-project/pull/153762