[llvm] b7ec10c - [AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instructions (#153880)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 15 17:18:45 PDT 2025
Author: Stanislav Mekhanoshin
Date: 2025-08-15T17:18:41-07:00
New Revision: b7ec10ca6c2a1d4825ce2e4058050c852c1b90c1
URL: https://github.com/llvm/llvm-project/commit/b7ec10ca6c2a1d4825ce2e4058050c852c1b90c1
DIFF: https://github.com/llvm/llvm-project/commit/b7ec10ca6c2a1d4825ce2e4058050c852c1b90c1.diff
LOG: [AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instructions (#153880)
This simply updates the pass's cognizance of these instructions, and for
the
most part the hazards where they might be encountered do not exist for
gfx12.
Nonetheless, encountering them has to be checked for as doing so would
indicate
a compiler error.
Co-authored-by: Stephen Thomas <Stephen.Thomas at amd.com>
---------
Co-authored-by: Stephen Thomas <Stephen.Thomas at amd.com>
Added:
Modified:
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index c1cca063aac6f..fa3ca27a5f47c 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1357,6 +1357,16 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
// DsCnt corresponds to LGKMCnt here.
return (Decoded.DsCnt == 0);
}
+ case AMDGPU::S_WAIT_STORECNT:
+ case AMDGPU::S_WAIT_STORECNT_DSCNT:
+ case AMDGPU::S_WAIT_LOADCNT:
+ case AMDGPU::S_WAIT_LOADCNT_DSCNT:
+ case AMDGPU::S_WAIT_SAMPLECNT:
+ case AMDGPU::S_WAIT_BVHCNT:
+ case AMDGPU::S_WAIT_DSCNT:
+ case AMDGPU::S_WAIT_EXPCNT:
+ case AMDGPU::S_WAIT_KMCNT:
+ llvm_unreachable("unexpected wait count instruction");
default:
// SOPP instructions cannot mitigate the hazard.
if (TII->isSOPP(MI))
@@ -2254,6 +2264,15 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
case AMDGPU::S_WAITCNT_EXPCNT:
case AMDGPU::S_WAITCNT_LGKMCNT:
case AMDGPU::S_WAIT_IDLE:
+ case AMDGPU::S_WAIT_LOADCNT:
+ case AMDGPU::S_WAIT_LOADCNT_DSCNT:
+ case AMDGPU::S_WAIT_SAMPLECNT:
+ case AMDGPU::S_WAIT_BVHCNT:
+ case AMDGPU::S_WAIT_STORECNT:
+ case AMDGPU::S_WAIT_STORECNT_DSCNT:
+ case AMDGPU::S_WAIT_EXPCNT:
+ case AMDGPU::S_WAIT_DSCNT:
+ case AMDGPU::S_WAIT_KMCNT:
return true;
default:
break;
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