[llvm] [Hexagon] Provide a custom decoder for Y4_crswap10 (PR #153849)

[Sergei Barannikov via llvm-commits]

s-barannikov wrote:

Another option would be to introduce a register class consisting only of `SGP1_0` only in this instruction and remove implicit defs/uses.
(We would still need to provide a custom decoder until TableGen disassembler backend is fixed, which is I'm currently working on.)
Does that sound better?


https://github.com/llvm/llvm-project/pull/153849