[llvm] [VectorCombine] Preserve scoped alias metadata (PR #153714)
Kyle Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 15 14:05:07 PDT 2025
https://github.com/knwng updated https://github.com/llvm/llvm-project/pull/153714
>From 25cbc66fb6931c346b7118599fb98a6158548908 Mon Sep 17 00:00:00 2001
From: Kyle Wang <ec1wng at gmail.com>
Date: Fri, 15 Aug 2025 00:13:52 +0000
Subject: [PATCH 1/2] Make VectorCombine Pass Alias Info
---
llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 4a681cbdab8ca..587889873a778 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -1811,6 +1811,10 @@ bool VectorCombine::scalarizeLoadExtract(Instruction &I) {
// erased in the correct order.
Worklist.push(LI);
+ LLVMContext &ctx = LI->getContext();
+ unsigned aliasScopeKind = ctx.getMDKindID("alias.scope");
+ unsigned noAliasKind = ctx.getMDKindID("noalias");
+
// Replace extracts with narrow scalar loads.
for (User *U : LI->users()) {
auto *EI = cast<ExtractElementInst>(U);
@@ -1831,6 +1835,14 @@ bool VectorCombine::scalarizeLoadExtract(Instruction &I) {
LI->getAlign(), VecTy->getElementType(), Idx, *DL);
NewLoad->setAlignment(ScalarOpAlignment);
+ if (MDNode *aliasScope = LI->getMetadata(aliasScopeKind)) {
+ NewLoad->setMetadata(aliasScopeKind, aliasScope);
+ }
+
+ if (MDNode *noAlias = LI->getMetadata(noAliasKind)) {
+ NewLoad->setMetadata(noAliasKind, noAlias);
+ }
+
replaceValue(*EI, *NewLoad);
}
>From adce7479712bc329a2453efc5fcdf999587b646f Mon Sep 17 00:00:00 2001
From: Kyle Wang <ec1wng at gmail.com>
Date: Fri, 15 Aug 2025 13:53:08 -0500
Subject: [PATCH 2/2] add test; address comments
---
.../Transforms/Vectorize/VectorCombine.cpp | 12 ++---
llvm/test/Transforms/VectorCombine/alias.ll | 49 +++++++++++++++++++
2 files changed, 53 insertions(+), 8 deletions(-)
create mode 100644 llvm/test/Transforms/VectorCombine/alias.ll
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index bfb71bc9c8294..c0d5d0cee6916 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -1805,10 +1805,6 @@ bool VectorCombine::scalarizeLoadExtract(Instruction &I) {
// erased in the correct order.
Worklist.push(LI);
- LLVMContext &ctx = LI->getContext();
- unsigned aliasScopeKind = ctx.getMDKindID("alias.scope");
- unsigned noAliasKind = ctx.getMDKindID("noalias");
-
// Replace extracts with narrow scalar loads.
for (User *U : LI->users()) {
auto *EI = cast<ExtractElementInst>(U);
@@ -1829,12 +1825,12 @@ bool VectorCombine::scalarizeLoadExtract(Instruction &I) {
LI->getAlign(), VecTy->getElementType(), Idx, *DL);
NewLoad->setAlignment(ScalarOpAlignment);
- if (MDNode *aliasScope = LI->getMetadata(aliasScopeKind)) {
- NewLoad->setMetadata(aliasScopeKind, aliasScope);
+ if (MDNode *aliasScope = LI->getMetadata(LLVMContext::MD_alias_scope)) {
+ NewLoad->setMetadata(LLVMContext::MD_alias_scope, aliasScope);
}
- if (MDNode *noAlias = LI->getMetadata(noAliasKind)) {
- NewLoad->setMetadata(noAliasKind, noAlias);
+ if (MDNode *noAlias = LI->getMetadata(LLVMContext::MD_noalias)) {
+ NewLoad->setMetadata(LLVMContext::MD_noalias, noAlias);
}
replaceValue(*EI, *NewLoad);
diff --git a/llvm/test/Transforms/VectorCombine/alias.ll b/llvm/test/Transforms/VectorCombine/alias.ll
new file mode 100644
index 0000000000000..e4cfb33e7a534
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/alias.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=vector-combine -S | FileCheck %s --check-prefixes=CHECK
+
+define <4 x i32> @quux(ptr addrspace(3) %arg) {
+; CHECK-LABEL: define <4 x i32> @quux(
+; CHECK-SAME: ptr addrspace(3) [[ARG:%.*]]) {
+; CHECK-NEXT: [[BB:.*:]]
+; CHECK-NEXT: [[EXTRACTELEMENT:%.*]] = load i8, ptr addrspace(3) [[ARG]], align 4, !alias.scope [[META0:![0-9]+]], !noalias [[META0]]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <4 x i8>, ptr addrspace(3) [[ARG]], i32 0, i64 1
+; CHECK-NEXT: [[EXTRACTELEMENT1:%.*]] = load i8, ptr addrspace(3) [[TMP0]], align 1, !alias.scope [[META0]], !noalias [[META0]]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x i8>, ptr addrspace(3) [[ARG]], i32 0, i64 2
+; CHECK-NEXT: [[EXTRACTELEMENT2:%.*]] = load i8, ptr addrspace(3) [[TMP1]], align 2, !alias.scope [[META0]], !noalias [[META0]]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds <4 x i8>, ptr addrspace(3) [[ARG]], i32 0, i64 3
+; CHECK-NEXT: [[EXTRACTELEMENT3:%.*]] = load i8, ptr addrspace(3) [[TMP2]], align 1, !alias.scope [[META0]], !noalias [[META0]]
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[EXTRACTELEMENT]] to i32
+; CHECK-NEXT: [[ZEXT4:%.*]] = zext i8 [[EXTRACTELEMENT1]] to i32
+; CHECK-NEXT: [[ZEXT5:%.*]] = zext i8 [[EXTRACTELEMENT2]] to i32
+; CHECK-NEXT: [[ZEXT6:%.*]] = zext i8 [[EXTRACTELEMENT3]] to i32
+; CHECK-NEXT: [[INSERTELEMENT:%.*]] = insertelement <4 x i32> poison, i32 [[ZEXT]], i64 0
+; CHECK-NEXT: [[INSERTELEMENT7:%.*]] = insertelement <4 x i32> [[INSERTELEMENT]], i32 [[ZEXT4]], i64 1
+; CHECK-NEXT: [[INSERTELEMENT8:%.*]] = insertelement <4 x i32> [[INSERTELEMENT7]], i32 [[ZEXT5]], i64 2
+; CHECK-NEXT: [[INSERTELEMENT9:%.*]] = insertelement <4 x i32> [[INSERTELEMENT8]], i32 [[ZEXT6]], i64 3
+; CHECK-NEXT: ret <4 x i32> [[INSERTELEMENT9]]
+;
+bb:
+ %load = load <4 x i8>, ptr addrspace(3) %arg, align 4, !alias.scope !0, !noalias !0
+ %extractelement = extractelement <4 x i8> %load, i64 0
+ %extractelement1 = extractelement <4 x i8> %load, i64 1
+ %extractelement2 = extractelement <4 x i8> %load, i64 2
+ %extractelement3 = extractelement <4 x i8> %load, i64 3
+ %zext = zext i8 %extractelement to i32
+ %zext4 = zext i8 %extractelement1 to i32
+ %zext5 = zext i8 %extractelement2 to i32
+ %zext6 = zext i8 %extractelement3 to i32
+ %insertelement = insertelement <4 x i32> poison, i32 %zext, i64 0
+ %insertelement7 = insertelement <4 x i32> %insertelement, i32 %zext4, i64 1
+ %insertelement8 = insertelement <4 x i32> %insertelement7, i32 %zext5, i64 2
+ %insertelement9 = insertelement <4 x i32> %insertelement8, i32 %zext6, i64 3
+ ret <4 x i32> %insertelement9
+}
+
+!0 = !{!1}
+!1 = distinct !{!1, !2}
+!2 = distinct !{!2}
+;.
+; CHECK: [[META0]] = !{[[META1:![0-9]+]]}
+; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
+; CHECK: [[META2]] = distinct !{[[META2]]}
+;.
\ No newline at end of file
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