[llvm] [RISCV][GlobalISel] Legalize and select G_ATOMICRMW_ADD instruction (PR #153791)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 15 08:23:28 PDT 2025
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@@ -1415,6 +1418,72 @@ void RISCVInstructionSelector::emitFence(AtomicOrdering FenceOrdering,
MIB.buildInstr(RISCV::FENCE, {}, {}).addImm(Pred).addImm(Succ);
}
+bool RISCVInstructionSelector::selectAtomicRMWAdd(MachineInstr &MI,
+ MachineIRBuilder &MIB) const {
+ MachineBasicBlock &MBB = *MI.getParent();
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topperc wrote:
Why aren't we able to import the patterns from tablegen?
https://github.com/llvm/llvm-project/pull/153791
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