[llvm] e2eaea4 - [RISCV] Add MC support for more P extension instructions. (#153629)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 14 23:23:31 PDT 2025
Author: Craig Topper
Date: 2025-08-14T23:23:28-07:00
New Revision: e2eaea412a379742146c5c94fbf328499699b139
URL: https://github.com/llvm/llvm-project/commit/e2eaea412a379742146c5c94fbf328499699b139
DIFF: https://github.com/llvm/llvm-project/commit/e2eaea412a379742146c5c94fbf328499699b139.diff
LOG: [RISCV] Add MC support for more P extension instructions. (#153629)
This implements pages 10-14 from
https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf
Test cases copied from #123271 with a couple mistakes fixed.
Co-authored-by: realqhc <caiqihan021 at hotmail.com>
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoP.td
llvm/test/MC/RISCV/rv32p-invalid.s
llvm/test/MC/RISCV/rv32p-valid.s
llvm/test/MC/RISCV/rv64p-invalid.s
llvm/test/MC/RISCV/rv64p-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index db3942b3ac7e7..e67417035963a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -149,6 +149,26 @@ class RVPBinaryScalar_rr<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr>
let Inst{26-25} = w;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinary_rr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
+ : RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd),
+ (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
+ let Inst{31} = 0b1;
+ let Inst{30-27} = f;
+ let Inst{26-25} = w;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPTernary_rrr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
+ : RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd_wb),
+ (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
+ let Inst{31} = 0b1;
+ let Inst{30-27} = f;
+ let Inst{26-25} = w;
+
+ let Constraints = "$rd = $rd_wb";
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -292,3 +312,250 @@ let Predicates = [HasStdExtP, IsRV64] in {
def PSRA_WS : RVPBinaryScalar_rr<0b100, 0b01, 0b100, "psra.ws">;
} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+ def PADD_H : RVPBinary_rr<0b0000, 0b00, 0b000, "padd.h">;
+ def PADD_B : RVPBinary_rr<0b0000, 0b10, 0b000, "padd.b">;
+
+ def PSADD_H : RVPBinary_rr<0b0010, 0b00, 0b000, "psadd.h">;
+ def PSADD_B : RVPBinary_rr<0b0010, 0b10, 0b000, "psadd.b">;
+
+ def PAADD_H : RVPBinary_rr<0b0011, 0b00, 0b000, "paadd.h">;
+ def PAADD_B : RVPBinary_rr<0b0011, 0b10, 0b000, "paadd.b">;
+
+ def PSADDU_H : RVPBinary_rr<0b0110, 0b00, 0b000, "psaddu.h">;
+ def PSADDU_B : RVPBinary_rr<0b0110, 0b10, 0b000, "psaddu.b">;
+
+ def PAADDU_H : RVPBinary_rr<0b0111, 0b00, 0b000, "paaddu.h">;
+ def PAADDU_B : RVPBinary_rr<0b0111, 0b10, 0b000, "paaddu.b">;
+
+ def PSUB_H : RVPBinary_rr<0b1000, 0b00, 0b000, "psub.h">;
+ def PSUB_B : RVPBinary_rr<0b1000, 0b10, 0b000, "psub.b">;
+
+ def PDIF_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pdif.h">;
+ def PDIF_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pdif.b">;
+
+ def PSSUB_H : RVPBinary_rr<0b1010, 0b00, 0b000, "pssub.h">;
+ def PSSUB_B : RVPBinary_rr<0b1010, 0b10, 0b000, "pssub.b">;
+
+ def PASUB_H : RVPBinary_rr<0b1011, 0b00, 0b000, "pasub.h">;
+ def PASUB_B : RVPBinary_rr<0b1011, 0b10, 0b000, "pasub.b">;
+
+ def PDIFU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pdifu.h">;
+ def PDIFU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pdifu.b">;
+
+ def PSSUBU_H : RVPBinary_rr<0b1110, 0b00, 0b000, "pssubu.h">;
+ def PSSUBU_B : RVPBinary_rr<0b1110, 0b10, 0b000, "pssubu.b">;
+
+ def PASUBU_H : RVPBinary_rr<0b1111, 0b00, 0b000, "pasubu.h">;
+ def PASUBU_B : RVPBinary_rr<0b1111, 0b10, 0b000, "pasubu.b">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def SADD : RVPBinary_rr<0b0010, 0b01, 0b000, "sadd">;
+
+ def AADD : RVPBinary_rr<0b0011, 0b01, 0b000, "aadd">;
+
+ def SADDU : RVPBinary_rr<0b0110, 0b01, 0b000, "saddu">;
+
+ def AADDU : RVPBinary_rr<0b0111, 0b01, 0b000, "aaddu">;
+
+ def SSUB : RVPBinary_rr<0b1010, 0b01, 0b000, "ssub">;
+
+ def ASUB : RVPBinary_rr<0b1011, 0b01, 0b000, "asub">;
+
+ def SSUBU : RVPBinary_rr<0b1110, 0b01, 0b000, "ssubu">;
+
+ def ASUBU : RVPBinary_rr<0b1111, 0b01, 0b000, "asubu">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PADD_W : RVPBinary_rr<0b0000, 0b01, 0b000, "padd.w">;
+
+ def PSADD_W : RVPBinary_rr<0b0010, 0b01, 0b000, "psadd.w">;
+
+ def PAADD_W : RVPBinary_rr<0b0011, 0b01, 0b000, "paadd.w">;
+
+ def PSADDU_W : RVPBinary_rr<0b0110, 0b01, 0b000, "psaddu.w">;
+
+ def PAADDU_W : RVPBinary_rr<0b0111, 0b01, 0b000, "paaddu.w">;
+
+ def PSUB_W : RVPBinary_rr<0b1000, 0b01, 0b000, "psub.w">;
+
+ def PSSUB_W : RVPBinary_rr<0b1010, 0b01, 0b000, "pssub.w">;
+
+ def PASUB_W : RVPBinary_rr<0b1011, 0b01, 0b000, "pasub.w">;
+
+ def PSSUBU_W : RVPBinary_rr<0b1110, 0b01, 0b000, "pssubu.w">;
+
+ def PASUBU_W : RVPBinary_rr<0b1111, 0b01, 0b000, "pasubu.w">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+ def SLX : RVPBinary_rr<0b0001, 0b11, 0b001, "slx">;
+
+ def PMUL_H_B01 : RVPBinary_rr<0b0010, 0b00, 0b001, "pmul.h.b01">;
+
+ def MVM : RVPTernary_rrr<0b0101, 0b00, 0b001, "mvm">;
+ def MVMN : RVPTernary_rrr<0b0101, 0b01, 0b001, "mvmn">;
+ def MERGE : RVPTernary_rrr<0b0101, 0b10, 0b001, "merge">;
+ def SRX : RVPTernary_rrr<0b0101, 0b11, 0b001, "srx">;
+
+ def PMULU_H_B01 : RVPBinary_rr<0b0110, 0b00, 0b001, "pmulu.h.b01">;
+ def PDIFSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pdifsumu.b">;
+
+ def PDIFSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pdifsumau.b">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def MUL_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "mul.h01">;
+
+ def MACC_H01 : RVPTernary_rrr<0b0011, 0b01, 0b001, "macc.h01">;
+
+ def MULU_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "mulu.h01">;
+
+ def MACCU_H01 : RVPTernary_rrr<0b0111, 0b01, 0b001, "maccu.h01">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PMUL_W_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "pmul.w.h01">;
+ def MUL_W01 : RVPBinary_rr<0b0010, 0b11, 0b001, "mul.w01">;
+
+ def PMACC_W_H01 : RVPTernary_rrr<0b0011, 0b01, 0b001, "pmacc.w.h01">;
+ def MACC_W01 : RVPTernary_rrr<0b0011, 0b11, 0b001, "macc.w01">;
+
+ def PMULU_W_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "pmulu.w.h01">;
+ def MULU_W01 : RVPBinary_rr<0b0110, 0b11, 0b001, "mulu.w01">;
+
+ def PMACCU_W_H01 : RVPTernary_rrr<0b0111, 0b01, 0b001, "pmaccu.w.h01">;
+ def MACCU_W01 : RVPTernary_rrr<0b0111, 0b11, 0b001, "maccu.w01">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.
+// Here we include the 0 in the f field to reduce number of tablegen classes.
+let Predicates = [HasStdExtP] in {
+ def PSH1ADD_H : RVPBinary_rr<0b0100, 0b00, 0b010, "psh1add.h">;
+
+ def PSSH1SADD_H : RVPBinary_rr<0b0110, 0b00, 0b010, "pssh1sadd.h">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def SSH1SADD : RVPBinary_rr<0b0110, 0b01, 0b010, "ssh1sadd">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PSH1ADD_W : RVPBinary_rr<0b0100, 0b01, 0b010, "psh1add.w">;
+
+ def PSSH1SADD_W : RVPBinary_rr<0b0110, 0b01, 0b010, "pssh1sadd.w">;
+
+ def UNZIP8P : RVPBinary_rr<0b1100, 0b00, 0b010, "unzip8p">;
+ def UNZIP16P : RVPBinary_rr<0b1100, 0b01, 0b010, "unzip16p">;
+ def UNZIP8HP : RVPBinary_rr<0b1100, 0b10, 0b010, "unzip8hp">;
+ def UNZIP16HP : RVPBinary_rr<0b1100, 0b11, 0b010, "unzip16hp">;
+
+ def ZIP8P : RVPBinary_rr<0b1110, 0b00, 0b010, "zip8p">;
+ def ZIP16P : RVPBinary_rr<0b1110, 0b01, 0b010, "zip16p">;
+ def ZIP8HP : RVPBinary_rr<0b1110, 0b10, 0b010, "zip8hp">;
+ def ZIP16HP : RVPBinary_rr<0b1110, 0b11, 0b010, "zip16hp">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+ def PMUL_H_B00 : RVPBinary_rr<0b0000, 0b00, 0b011, "pmul.h.b00">;
+
+ def PMUL_H_B11 : RVPBinary_rr<0b0010, 0b00, 0b011, "pmul.h.b11">;
+
+ def PMULU_H_B00 : RVPBinary_rr<0b0100, 0b00, 0b011, "pmulu.h.b00">;
+
+ def PMULU_H_B11 : RVPBinary_rr<0b0110, 0b00, 0b011, "pmulu.h.b11">;
+
+ def PMULSU_H_B00 : RVPBinary_rr<0b1100, 0b00, 0b011, "pmulsu.h.b00">;
+
+ def PMULSU_H_B11 : RVPBinary_rr<0b1110, 0b00, 0b011, "pmulsu.h.b11">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def MUL_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "mul.h00">;
+
+ def MACC_H00 : RVPTernary_rrr<0b0001, 0b01, 0b011, "macc.h00">;
+
+ def MUL_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "mul.h11">;
+
+ def MACC_H11 : RVPTernary_rrr<0b0011, 0b01, 0b011, "macc.h11">;
+
+ def MULU_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "mulu.h00">;
+
+ def MACCU_H00 : RVPTernary_rrr<0b0101, 0b01, 0b011, "maccu.h00">;
+
+ def MULU_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "mulu.h11">;
+
+ def MACCU_H11 : RVPTernary_rrr<0b0111, 0b01, 0b011, "maccu.h11">;
+
+ def MULSU_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "mulsu.h00">;
+
+ def MACCSU_H00 : RVPTernary_rrr<0b1101, 0b01, 0b011, "maccsu.h00">;
+
+ def MULSU_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "mulsu.h11">;
+
+ def MACCSU_H11 : RVPTernary_rrr<0b1111, 0b01, 0b011, "maccsu.h11">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PMUL_W_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "pmul.w.h00">;
+ def MUL_W00 : RVPBinary_rr<0b0000, 0b11, 0b011, "mul.w00">;
+
+ def PMACC_W_H00 : RVPTernary_rrr<0b0001, 0b01, 0b011, "pmacc.w.h00">;
+ def MACC_W00 : RVPTernary_rrr<0b0001, 0b11, 0b011, "macc.w00">;
+
+ def PMUL_W_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "pmul.w.h11">;
+ def MUL_W11 : RVPBinary_rr<0b0010, 0b11, 0b011, "mul.w11">;
+
+ def PMACC_W_H11 : RVPTernary_rrr<0b0011, 0b01, 0b011, "pmacc.w.h11">;
+ def MACC_W11 : RVPTernary_rrr<0b0011, 0b11, 0b011, "macc.w11">;
+
+ def PMULU_W_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "pmulu.w.h00">;
+ def MULU_W00 : RVPBinary_rr<0b0100, 0b11, 0b011, "mulu.w00">;
+
+ def PMACCU_W_H00 : RVPTernary_rrr<0b0101, 0b01, 0b011, "pmaccu.w.h00">;
+ def MACCU_W00 : RVPTernary_rrr<0b0101, 0b11, 0b011, "maccu.w00">;
+
+ def PMULU_W_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "pmulu.w.h11">;
+ def MULU_W11 : RVPBinary_rr<0b0110, 0b11, 0b011, "mulu.w11">;
+
+ def PMACCU_W_H11 : RVPTernary_rrr<0b0111, 0b01, 0b011, "pmaccu.w.h11">;
+ def MACCU_W11 : RVPTernary_rrr<0b0111, 0b11, 0b011, "maccu.w11">;
+
+ def PMULSU_W_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "pmulsu.w.h00">;
+ def MULSU_W00 : RVPBinary_rr<0b1100, 0b11, 0b011, "mulsu.w00">;
+
+ def PMACCSU_W_H00 : RVPTernary_rrr<0b1101, 0b01, 0b011, "pmaccsu.w.h00">;
+ def MACCSU_W00 : RVPTernary_rrr<0b1101, 0b11, 0b011, "maccsu.w00">;
+
+ def PMULSU_W_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "pmulsu.w.h11">;
+ def MULSU_W11 : RVPBinary_rr<0b1110, 0b11, 0b011, "mulsu.w11">;
+
+ def PMACCSU_W_H11 : RVPTernary_rrr<0b1111, 0b01, 0b011, "pmaccsu.w.h11">;
+ def MACCSU_W11 : RVPTernary_rrr<0b1111, 0b11, 0b011, "maccsu.w11">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.
+// Here we include the 0 in the f field to reduce number of tablegen classes.
+let Predicates = [HasStdExtP] in {
+ def PPACK_H : RVPBinary_rr<0b0000, 0b00, 0b100, "ppack.h">;
+
+ def PPACKBT_H : RVPBinary_rr<0b0010, 0b00, 0b100, "ppackbt.h">;
+
+ def PPACKTB_H : RVPBinary_rr<0b0100, 0b00, 0b100, "ppacktb.h">;
+
+ def PPACKT_H : RVPBinary_rr<0b0110, 0b00, 0b100, "ppackt.h">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def PACKBT_RV32 : RVPBinary_rr<0b0010, 0b01, 0b100, "packbt">;
+
+ def PACKTB_RV32 : RVPBinary_rr<0b0100, 0b01, 0b100, "packtb">;
+
+ def PACKT_RV32 : RVPBinary_rr<0b0110, 0b01, 0b100, "packt">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PPACK_W : RVPBinary_rr<0b0000, 0b01, 0b100, "ppack.w">;
+
+ def PPACKBT_W : RVPBinary_rr<0b0010, 0b01, 0b100, "ppackbt.w">;
+ def PACKBT_RV64 : RVPBinary_rr<0b0010, 0b11, 0b100, "packbt">;
+
+ def PPACKTB_W : RVPBinary_rr<0b0100, 0b01, 0b100, "ppacktb.w">;
+ def PACKTB_RV64 : RVPBinary_rr<0b0100, 0b11, 0b100, "packtb">;
+
+ def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;
+ def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;
+} // Predicates = [HasStdExtP, IsRV64]
diff --git a/llvm/test/MC/RISCV/rv32p-invalid.s b/llvm/test/MC/RISCV/rv32p-invalid.s
index ebd2d21b7fcf4..7dd73d077bf3a 100644
--- a/llvm/test/MC/RISCV/rv32p-invalid.s
+++ b/llvm/test/MC/RISCV/rv32p-invalid.s
@@ -45,3 +45,64 @@ psrl.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the follow
predsum.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
predsumu.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
psra.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+padd.w t3, s0, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+psadd.w t3, t1, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+paadd.w t5, t1, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+psaddu.w s0, s2, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+paaddu.w s0, t1, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+psub.w t3, a0, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pssub.w t3, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pasub.w t3, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pssubu.w a0, a4, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pasubu.w a0, t3, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+pmul.w.h01 s2, t5, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mul.w01 t5, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmacc.w.h01 t1, t1, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+macc.w01 s2, a0, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulu.w.h01 t1, a4, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulu.w01 t5, t1, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccu.w.h01 t5, t5, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccu.w01 a0, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+psh1add.w s2, t5, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pssh1sadd.w a4, t3, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip8p a4, t3, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip16p t5, a4, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip8hp s0, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip16hp a0, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip8p t5, t3, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip16p a0, t5, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip8hp t5, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip16hp t1, t5, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+pmul.w.h00 s2, t1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mul.w00 a4, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmacc.w.h00 s2, t5, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+macc.w00 t1, a0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmul.w.h11 s0, a4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mul.w11 a0, t3, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmacc.w.h11 a4, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+macc.w11 t3, s2, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulu.w.h00 a2, t3, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulu.w00 a0, t5, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccu.w.h00 t3, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccu.w00 s2, t1, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulu.w.h11 s0, t5, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulu.w11 s0, t1, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccu.w.h11 a0, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccu.w11 s2, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulsu.w.h00 t5, t5, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulsu.w00 t1, s0, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulsu.w.h11 t1, t3, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulsu.w11 a2, s2, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccsu.w.h00 a4, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccsu.w00 a4, s2, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccsu.w.h11 a0, a2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccsu.w11 t5, a4, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+ppack.w t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+ppackbt.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+ppacktb.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+ppackt.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s
index 3e65fef1524f4..0383e4ec1ea62 100644
--- a/llvm/test/MC/RISCV/rv32p-valid.s
+++ b/llvm/test/MC/RISCV/rv32p-valid.s
@@ -154,3 +154,222 @@ psra.hs ra, a1, a2
# CHECK-ASM-AND-OBJ: psra.bs sp, a2, a3
# CHECK-ASM: encoding: [0x1b,0x41,0xd6,0xcc]
psra.bs sp, a2, a3
+# CHECK-ASM-AND-OBJ: padd.h t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x80]
+padd.h t0, t1, t2
+# CHECK-ASM-AND-OBJ: padd.b ra, a1, a2
+# CHECK-ASM: encoding: [0xbb,0x80,0xc5,0x84]
+padd.b ra, a1, a2
+# CHECK-ASM-AND-OBJ: psadd.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0x91]
+psadd.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: sadd t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0x92]
+sadd t1, a7, a0
+# CHECK-ASM-AND-OBJ: psadd.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x94]
+psadd.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: paadd.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0x99]
+paadd.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: aadd t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0x9a]
+aadd t1, a7, a0
+# CHECK-ASM-AND-OBJ: paadd.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x9c]
+paadd.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: psaddu.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xb1]
+psaddu.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: saddu t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0xb2]
+saddu t1, a7, a0
+# CHECK-ASM-AND-OBJ: psaddu.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xb4]
+psaddu.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: paaddu.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xb9]
+paaddu.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: aaddu t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0xba]
+aaddu t1, a7, a0
+# CHECK-ASM-AND-OBJ: paaddu.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xbc]
+paaddu.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: psub.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xc1]
+psub.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: psub.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xc4]
+psub.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: pdif.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xc9]
+pdif.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: pdif.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xcc]
+pdif.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: pssub.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xd1]
+pssub.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: ssub t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0xd2]
+ssub t1, a7, a0
+# CHECK-ASM-AND-OBJ: pssub.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xd4]
+pssub.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: pasub.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xd9]
+pasub.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: asub t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0xda]
+asub t1, a7, a0
+# CHECK-ASM-AND-OBJ: pasub.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xdc]
+pasub.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: pdifu.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xe9]
+pdifu.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: pdifu.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xec]
+pdifu.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: pssubu.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xf1]
+pssubu.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: ssubu t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0xf2]
+ssubu t1, a7, a0
+# CHECK-ASM-AND-OBJ: pssubu.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xf4]
+pssubu.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: pasubu.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xf9]
+pasubu.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: asubu t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0xfa]
+asubu t1, a7, a0
+# CHECK-ASM-AND-OBJ: pasubu.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0xfc]
+pasubu.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: slx gp, a4, a5
+# CHECK-ASM: encoding: [0xbb,0x11,0xf7,0x8e]
+slx gp, a4, a5
+# CHECK-ASM-AND-OBJ: pmul.h.b01 t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x9e,0xee,0x91]
+pmul.h.b01 t3, t4, t5
+# CHECK-ASM-AND-OBJ: mul.h01 t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x92]
+mul.h01 t0, t1, t2
+# CHECK-ASM-AND-OBJ: macc.h01 t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x9e,0xee,0x9b]
+macc.h01 t3, t4, t5
+# CHECK-ASM-AND-OBJ: mvm a0, a1, a2
+# CHECK-ASM: encoding: [0x3b,0x95,0xc5,0xa8]
+mvm a0, a1, a2
+# CHECK-ASM-AND-OBJ: mvmn gp, a4, a5
+# CHECK-ASM: encoding: [0xbb,0x11,0xf7,0xaa]
+mvmn gp, a4, a5
+# CHECK-ASM-AND-OBJ: merge t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0xac]
+merge t0, t1, t2
+# CHECK-ASM-AND-OBJ: srx gp, a4, a5
+# CHECK-ASM: encoding: [0xbb,0x11,0xf7,0xae]
+srx gp, a4, a5
+# CHECK-ASM-AND-OBJ: pmulu.h.b01 t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x9e,0xee,0xb1]
+pmulu.h.b01 t3, t4, t5
+# CHECK-ASM-AND-OBJ: mulu.h01 t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0xb2]
+mulu.h01 t0, t1, t2
+# CHECK-ASM-AND-OBJ: pdifsumu.b t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x9e,0xee,0xb5]
+pdifsumu.b t3, t4, t5
+# CHECK-ASM-AND-OBJ: maccu.h01 t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x9e,0xee,0xbb]
+maccu.h01 t3, t4, t5
+# CHECK-ASM-AND-OBJ: pdifsumau.b t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x9e,0xee,0xbd]
+pdifsumau.b t3, t4, t5
+# CHECK-ASM-AND-OBJ: psh1add.h a0, a1, a2
+# CHECK-ASM: encoding: [0x3b,0xa5,0xc5,0xa0]
+psh1add.h a0, a1, a2
+# CHECK-ASM-AND-OBJ: pssh1sadd.h a3, a4, a5
+# CHECK-ASM: encoding: [0xbb,0x26,0xf7,0xb0]
+pssh1sadd.h a3, a4, a5
+# CHECK-ASM-AND-OBJ: ssh1sadd t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x22,0x73,0xb2]
+ssh1sadd t0, t1, t2
+# CHECK-ASM-AND-OBJ: pmul.h.b00 s6, t4, s8
+# CHECK-ASM: encoding: [0x3b,0xbb,0x8e,0x81]
+pmul.h.b00 s6, t4, s8
+# CHECK-ASM-AND-OBJ: mul.h00 a4, t4, s2
+# CHECK-ASM: encoding: [0x3b,0xb7,0x2e,0x83]
+mul.h00 a4, t4, s2
+# CHECK-ASM-AND-OBJ: macc.h00 a4, a0, s0
+# CHECK-ASM: encoding: [0x3b,0x37,0x85,0x8a]
+macc.h00 a4, a0, s0
+# CHECK-ASM-AND-OBJ: pmul.h.b11 t0, t4, s4
+# CHECK-ASM: encoding: [0xbb,0xb2,0x4e,0x91]
+pmul.h.b11 t0, t4, s4
+# CHECK-ASM-AND-OBJ: mul.h11 a0, a4, a0
+# CHECK-ASM: encoding: [0x3b,0x35,0xa7,0x92]
+mul.h11 a0, a4, a0
+# CHECK-ASM-AND-OBJ: macc.h11 s6, a4, s4
+# CHECK-ASM: encoding: [0x3b,0x3b,0x47,0x9b]
+macc.h11 s6, a4, s4
+# CHECK-ASM-AND-OBJ: pmulu.h.b00 t2, s6, s8
+# CHECK-ASM: encoding: [0xbb,0x33,0x8b,0xa1]
+pmulu.h.b00 t2, s6, s8
+# CHECK-ASM-AND-OBJ: mulu.h00 s6, s0, a0
+# CHECK-ASM: encoding: [0x3b,0x3b,0xa4,0xa2]
+mulu.h00 s6, s0, a0
+# CHECK-ASM-AND-OBJ: maccu.h00 s0, s6, s0
+# CHECK-ASM: encoding: [0x3b,0x34,0x8b,0xaa]
+maccu.h00 s0, s6, s0
+# CHECK-ASM-AND-OBJ: pmulu.h.b11 t2, s6, a0
+# CHECK-ASM: encoding: [0xbb,0x33,0xab,0xb0]
+pmulu.h.b11 t2, s6, a0
+# CHECK-ASM-AND-OBJ: mulu.h11 s0, s4, s6
+# CHECK-ASM: encoding: [0x3b,0x34,0x6a,0xb3]
+mulu.h11 s0, s4, s6
+# CHECK-ASM-AND-OBJ: maccu.h11 s0, t4, t4
+# CHECK-ASM: encoding: [0x3b,0xb4,0xde,0xbb]
+maccu.h11 s0, t4, t4
+# CHECK-ASM-AND-OBJ: pmulsu.h.b00 s4, a4, s8
+# CHECK-ASM: encoding: [0x3b,0x3a,0x87,0xe1]
+pmulsu.h.b00 s4, a4, s8
+# CHECK-ASM-AND-OBJ: mulsu.h00 a4, s4, s6
+# CHECK-ASM: encoding: [0x3b,0x37,0x6a,0xe3]
+mulsu.h00 a4, s4, s6
+# CHECK-ASM-AND-OBJ: maccsu.h00 s4, s4, s0
+# CHECK-ASM: encoding: [0x3b,0x3a,0x8a,0xea]
+maccsu.h00 s4, s4, s0
+# CHECK-ASM-AND-OBJ: pmulsu.h.b11 s6, a2, s4
+# CHECK-ASM: encoding: [0x3b,0x3b,0x46,0xf1]
+pmulsu.h.b11 s6, a2, s4
+# CHECK-ASM-AND-OBJ: mulsu.h11 s8, s4, s0
+# CHECK-ASM: encoding: [0x3b,0x3c,0x8a,0xf2]
+mulsu.h11 s8, s4, s0
+# CHECK-ASM-AND-OBJ: maccsu.h11 s0, a2, s6
+# CHECK-ASM: encoding: [0x3b,0x34,0x66,0xfb]
+maccsu.h11 s0, a2, s6
+# CHECK-ASM-AND-OBJ: ppack.h t1, a2, t5
+# CHECK-ASM: encoding: [0x3b,0x43,0xe6,0x81]
+ppack.h t1, a2, t5
+# CHECK-ASM-AND-OBJ: ppackbt.h t5, t3, s2
+# CHECK-ASM: encoding: [0x3b,0x4f,0x2e,0x91]
+ppackbt.h t5, t3, s2
+# CHECK-ASM-AND-OBJ: packbt t1, t1, s2
+# CHECK-ASM: encoding: [0x3b,0x43,0x23,0x93]
+packbt t1, t1, s2
+# CHECK-ASM-AND-OBJ: ppacktb.h t1, t1, s0
+# CHECK-ASM: encoding: [0x3b,0x43,0x83,0xa0]
+ppacktb.h t1, t1, s0
+# CHECK-ASM-AND-OBJ: packtb t5, s0, a2
+# CHECK-ASM: encoding: [0x3b,0x4f,0xc4,0xa2]
+packtb t5, s0, a2
+# CHECK-ASM-AND-OBJ: ppackt.h t3, s0, s0
+# CHECK-ASM: encoding: [0x3b,0x4e,0x84,0xb0]
+ppackt.h t3, s0, s0
+# CHECK-ASM-AND-OBJ: packt a2, t3, t1
+# CHECK-ASM: encoding: [0x3b,0x46,0x6e,0xb2]
+packt a2, t3, t1
diff --git a/llvm/test/MC/RISCV/rv64p-invalid.s b/llvm/test/MC/RISCV/rv64p-invalid.s
index 0d7b12e3ad6ef..58f5dfb822dea 100644
--- a/llvm/test/MC/RISCV/rv64p-invalid.s
+++ b/llvm/test/MC/RISCV/rv64p-invalid.s
@@ -36,3 +36,32 @@ srari ra, sp, 100 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in
psati.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15]
psati.w ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
sati ra, sp, 100 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 63]
+
+sadd t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+aadd t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+saddu t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+aaddu t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+ssub t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+asub t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+ssubu t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+asubu t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+
+mul.h01 t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+macc.h01 t3, t4, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+mulu.h01 t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+maccu.h01 t3, t4, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+
+ssh1sadd t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+
+mul.h00 a4, t4, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+macc.h00 a4, a0, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+mul.h11 a0, a4, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+macc.h11 s6, a4, s4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+mulu.h00 s6, s0, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+maccu.h00 s0, s6, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+mulu.h11 s0, s4, s6 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+maccu.h11 s0, t4, t4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+mulsu.h00 a4, s4, s6 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+maccsu.h00 s4, s4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+mulsu.h11 s8, s4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
+maccsu.h11 s0, a2, s6 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s
index 95dd16bed627b..5e0b22759abf4 100644
--- a/llvm/test/MC/RISCV/rv64p-valid.s
+++ b/llvm/test/MC/RISCV/rv64p-valid.s
@@ -211,3 +211,315 @@ psra.hs ra, a1, a2
# CHECK-ASM-AND-OBJ: psra.bs sp, a2, a3
# CHECK-ASM: encoding: [0x1b,0x41,0xd6,0xcc]
psra.bs sp, a2, a3
+# CHECK-ASM-AND-OBJ: padd.h t1, t5, s2
+# CHECK-ASM: encoding: [0x3b,0x03,0x2f,0x81]
+padd.h t1, t5, s2
+# CHECK-ASM-AND-OBJ: padd.w t3, s0, a0
+# CHECK-ASM: encoding: [0x3b,0x0e,0xa4,0x82]
+padd.w t3, s0, a0
+# CHECK-ASM-AND-OBJ: padd.b t5, s0, t1
+# CHECK-ASM: encoding: [0x3b,0x0f,0x64,0x84]
+padd.b t5, s0, t1
+# CHECK-ASM-AND-OBJ: psadd.h a2, a2, s2
+# CHECK-ASM: encoding: [0x3b,0x06,0x26,0x91]
+psadd.h a2, a2, s2
+# CHECK-ASM-AND-OBJ: psadd.w t3, t1, s2
+# CHECK-ASM: encoding: [0x3b,0x0e,0x23,0x93]
+psadd.w t3, t1, s2
+# CHECK-ASM-AND-OBJ: psadd.b t1, a0, s0
+# CHECK-ASM: encoding: [0x3b,0x03,0x85,0x94]
+psadd.b t1, a0, s0
+# CHECK-ASM-AND-OBJ: paadd.h t5, s0, t3
+# CHECK-ASM: encoding: [0x3b,0x0f,0xc4,0x99]
+paadd.h t5, s0, t3
+# CHECK-ASM-AND-OBJ: paadd.w t5, t1, a4
+# CHECK-ASM: encoding: [0x3b,0x0f,0xe3,0x9a]
+paadd.w t5, t1, a4
+# CHECK-ASM-AND-OBJ: paadd.b a4, s2, a4
+# CHECK-ASM: encoding: [0x3b,0x07,0xe9,0x9c]
+paadd.b a4, s2, a4
+# CHECK-ASM-AND-OBJ: psaddu.h a0, t1, t1
+# CHECK-ASM: encoding: [0x3b,0x05,0x63,0xb0]
+psaddu.h a0, t1, t1
+# CHECK-ASM-AND-OBJ: psaddu.w s0, s2, t5
+# CHECK-ASM: encoding: [0x3b,0x04,0xe9,0xb3]
+psaddu.w s0, s2, t5
+# CHECK-ASM-AND-OBJ: psaddu.b t3, a2, a4
+# CHECK-ASM: encoding: [0x3b,0x0e,0xe6,0xb4]
+psaddu.b t3, a2, a4
+# CHECK-ASM-AND-OBJ: paaddu.h t3, s2, a2
+# CHECK-ASM: encoding: [0x3b,0x0e,0xc9,0xb8]
+paaddu.h t3, s2, a2
+# CHECK-ASM-AND-OBJ: paaddu.w s0, t1, s0
+# CHECK-ASM: encoding: [0x3b,0x04,0x83,0xba]
+paaddu.w s0, t1, s0
+# CHECK-ASM-AND-OBJ: paaddu.b t3, a0, t3
+# CHECK-ASM: encoding: [0x3b,0x0e,0xc5,0xbd]
+paaddu.b t3, a0, t3
+# CHECK-ASM-AND-OBJ: psub.h s0, s2, t3
+# CHECK-ASM: encoding: [0x3b,0x04,0xc9,0xc1]
+psub.h s0, s2, t3
+# CHECK-ASM-AND-OBJ: psub.w t3, a0, s0
+# CHECK-ASM: encoding: [0x3b,0x0e,0x85,0xc2]
+psub.w t3, a0, s0
+# CHECK-ASM-AND-OBJ: psub.b t5, t1, a4
+# CHECK-ASM: encoding: [0x3b,0x0f,0xe3,0xc4]
+psub.b t5, t1, a4
+# CHECK-ASM-AND-OBJ: pdif.h t1, a4, a2
+# CHECK-ASM: encoding: [0x3b,0x03,0xc7,0xc8]
+pdif.h t1, a4, a2
+# CHECK-ASM-AND-OBJ: pdif.b t3, t1, t5
+# CHECK-ASM: encoding: [0x3b,0x0e,0xe3,0xcd]
+pdif.b t3, t1, t5
+# CHECK-ASM-AND-OBJ: pssub.h a0, a2, t3
+# CHECK-ASM: encoding: [0x3b,0x05,0xc6,0xd1]
+pssub.h a0, a2, t3
+# CHECK-ASM-AND-OBJ: pssub.w t3, a4, t1
+# CHECK-ASM: encoding: [0x3b,0x0e,0x67,0xd2]
+pssub.w t3, a4, t1
+# CHECK-ASM-AND-OBJ: pssub.b a2, t5, a4
+# CHECK-ASM: encoding: [0x3b,0x06,0xef,0xd4]
+pssub.b a2, t5, a4
+# CHECK-ASM-AND-OBJ: pasub.h t5, t3, t3
+# CHECK-ASM: encoding: [0x3b,0x0f,0xce,0xd9]
+pasub.h t5, t3, t3
+# CHECK-ASM-AND-OBJ: pasub.w t3, a2, a4
+# CHECK-ASM: encoding: [0x3b,0x0e,0xe6,0xda]
+pasub.w t3, a2, a4
+# CHECK-ASM-AND-OBJ: pasub.b s0, t3, s2
+# CHECK-ASM: encoding: [0x3b,0x04,0x2e,0xdd]
+pasub.b s0, t3, s2
+# CHECK-ASM-AND-OBJ: pdifu.h t5, s0, a4
+# CHECK-ASM: encoding: [0x3b,0x0f,0xe4,0xe8]
+pdifu.h t5, s0, a4
+# CHECK-ASM-AND-OBJ: pdifu.b t3, a0, t5
+# CHECK-ASM: encoding: [0x3b,0x0e,0xe5,0xed]
+pdifu.b t3, a0, t5
+# CHECK-ASM-AND-OBJ: pssubu.h t3, s2, a0
+# CHECK-ASM: encoding: [0x3b,0x0e,0xa9,0xf0]
+pssubu.h t3, s2, a0
+# CHECK-ASM-AND-OBJ: pssubu.w a0, a4, t3
+# CHECK-ASM: encoding: [0x3b,0x05,0xc7,0xf3]
+pssubu.w a0, a4, t3
+# CHECK-ASM-AND-OBJ: pssubu.b t3, a4, t3
+# CHECK-ASM: encoding: [0x3b,0x0e,0xc7,0xf5]
+pssubu.b t3, a4, t3
+# CHECK-ASM-AND-OBJ: pasubu.h a2, s0, t5
+# CHECK-ASM: encoding: [0x3b,0x06,0xe4,0xf9]
+pasubu.h a2, s0, t5
+# CHECK-ASM-AND-OBJ: pasubu.w a0, t3, a4
+# CHECK-ASM: encoding: [0x3b,0x05,0xee,0xfa]
+pasubu.w a0, t3, a4
+# CHECK-ASM-AND-OBJ: pasubu.b s0, t5, a4
+# CHECK-ASM: encoding: [0x3b,0x04,0xef,0xfc]
+pasubu.b s0, t5, a4
+# CHECK-ASM-AND-OBJ: slx a0, a2, s2
+# CHECK-ASM: encoding: [0x3b,0x15,0x26,0x8f]
+slx a0, a2, s2
+# CHECK-ASM-AND-OBJ: pmul.h.b01 a2, a4, a2
+# CHECK-ASM: encoding: [0x3b,0x16,0xc7,0x90]
+pmul.h.b01 a2, a4, a2
+# CHECK-ASM-AND-OBJ: pmul.w.h01 s2, t5, t3
+# CHECK-ASM: encoding: [0x3b,0x19,0xcf,0x93]
+pmul.w.h01 s2, t5, t3
+# CHECK-ASM-AND-OBJ: mul.w01 t5, a4, t1
+# CHECK-ASM: encoding: [0x3b,0x1f,0x67,0x96]
+mul.w01 t5, a4, t1
+# CHECK-ASM-AND-OBJ: pmacc.w.h01 t1, t1, a0
+# CHECK-ASM: encoding: [0x3b,0x13,0xa3,0x9a]
+pmacc.w.h01 t1, t1, a0
+# CHECK-ASM-AND-OBJ: macc.w01 s2, a0, t3
+# CHECK-ASM: encoding: [0x3b,0x19,0xc5,0x9f]
+macc.w01 s2, a0, t3
+# CHECK-ASM-AND-OBJ: mvm s0, t1, a2
+# CHECK-ASM: encoding: [0x3b,0x14,0xc3,0xa8]
+mvm s0, t1, a2
+# CHECK-ASM-AND-OBJ: mvmn a2, a4, a0
+# CHECK-ASM: encoding: [0x3b,0x16,0xa7,0xaa]
+mvmn a2, a4, a0
+# CHECK-ASM-AND-OBJ: merge a4, a2, a2
+# CHECK-ASM: encoding: [0x3b,0x17,0xc6,0xac]
+merge a4, a2, a2
+# CHECK-ASM-AND-OBJ: srx t1, t3, a4
+# CHECK-ASM: encoding: [0x3b,0x13,0xee,0xae]
+srx t1, t3, a4
+# CHECK-ASM-AND-OBJ: pmulu.h.b01 s2, a4, a0
+# CHECK-ASM: encoding: [0x3b,0x19,0xa7,0xb0]
+pmulu.h.b01 s2, a4, a0
+# CHECK-ASM-AND-OBJ: pmulu.w.h01 t1, a4, a2
+# CHECK-ASM: encoding: [0x3b,0x13,0xc7,0xb2]
+pmulu.w.h01 t1, a4, a2
+# CHECK-ASM-AND-OBJ: pdifsumu.b t3, t5, t3
+# CHECK-ASM: encoding: [0x3b,0x1e,0xcf,0xb5]
+pdifsumu.b t3, t5, t3
+# CHECK-ASM-AND-OBJ: mulu.w01 t5, t1, t5
+# CHECK-ASM: encoding: [0x3b,0x1f,0xe3,0xb7]
+mulu.w01 t5, t1, t5
+# CHECK-ASM-AND-OBJ: pmaccu.w.h01 t5, t5, a4
+# CHECK-ASM: encoding: [0x3b,0x1f,0xef,0xba]
+pmaccu.w.h01 t5, t5, a4
+# CHECK-ASM-AND-OBJ: pdifsumau.b s2, a2, a0
+# CHECK-ASM: encoding: [0x3b,0x19,0xa6,0xbc]
+pdifsumau.b s2, a2, a0
+# CHECK-ASM-AND-OBJ: maccu.w01 a0, a0, t1
+# CHECK-ASM: encoding: [0x3b,0x15,0x65,0xbe]
+maccu.w01 a0, a0, t1
+# CHECK-ASM-AND-OBJ: psh1add.h a2, a2, t3
+# CHECK-ASM: encoding: [0x3b,0x26,0xc6,0xa1]
+psh1add.h a2, a2, t3
+# CHECK-ASM-AND-OBJ: pssh1sadd.h a2, t3, t3
+# CHECK-ASM: encoding: [0x3b,0x26,0xce,0xb1]
+pssh1sadd.h a2, t3, t3
+# CHECK-ASM-AND-OBJ: psh1add.w s2, t5, a2
+# CHECK-ASM: encoding: [0x3b,0x29,0xcf,0xa2]
+psh1add.w s2, t5, a2
+# CHECK-ASM-AND-OBJ: pssh1sadd.w a4, t3, s0
+# CHECK-ASM: encoding: [0x3b,0x27,0x8e,0xb2]
+pssh1sadd.w a4, t3, s0
+# CHECK-ASM-AND-OBJ: unzip8p a4, t3, t1
+# CHECK-ASM: encoding: [0x3b,0x27,0x6e,0xe0]
+unzip8p a4, t3, t1
+# CHECK-ASM-AND-OBJ: unzip16p t5, a4, t3
+# CHECK-ASM: encoding: [0x3b,0x2f,0xc7,0xe3]
+unzip16p t5, a4, t3
+# CHECK-ASM-AND-OBJ: unzip8hp s0, a0, t1
+# CHECK-ASM: encoding: [0x3b,0x24,0x65,0xe4]
+unzip8hp s0, a0, t1
+# CHECK-ASM-AND-OBJ: unzip16hp a0, a0, a2
+# CHECK-ASM: encoding: [0x3b,0x25,0xc5,0xe6]
+unzip16hp a0, a0, a2
+# CHECK-ASM-AND-OBJ: zip8p t5, t3, t3
+# CHECK-ASM: encoding: [0x3b,0x2f,0xce,0xf1]
+zip8p t5, t3, t3
+# CHECK-ASM-AND-OBJ: zip16p a0, t5, a0
+# CHECK-ASM: encoding: [0x3b,0x25,0xaf,0xf2]
+zip16p a0, t5, a0
+# CHECK-ASM-AND-OBJ: zip8hp t5, a0, a2
+# CHECK-ASM: encoding: [0x3b,0x2f,0xc5,0xf4]
+zip8hp t5, a0, a2
+# CHECK-ASM-AND-OBJ: zip16hp t1, t5, a4
+# CHECK-ASM: encoding: [0x3b,0x23,0xef,0xf6]
+zip16hp t1, t5, a4
+# CHECK-ASM-AND-OBJ: pmul.h.b00 a4, a4, s2
+# CHECK-ASM: encoding: [0x3b,0x37,0x27,0x81]
+pmul.h.b00 a4, a4, s2
+# CHECK-ASM-AND-OBJ: pmul.w.h00 s2, t1, a2
+# CHECK-ASM: encoding: [0x3b,0x39,0xc3,0x82]
+pmul.w.h00 s2, t1, a2
+# CHECK-ASM-AND-OBJ: mul.w00 a4, a0, a2
+# CHECK-ASM: encoding: [0x3b,0x37,0xc5,0x86]
+mul.w00 a4, a0, a2
+# CHECK-ASM-AND-OBJ: pmacc.w.h00 s2, t5, a2
+# CHECK-ASM: encoding: [0x3b,0x39,0xcf,0x8a]
+pmacc.w.h00 s2, t5, a2
+# CHECK-ASM-AND-OBJ: macc.w00 t1, a0, t5
+# CHECK-ASM: encoding: [0x3b,0x33,0xe5,0x8f]
+macc.w00 t1, a0, t5
+# CHECK-ASM-AND-OBJ: pmul.h.b11 t1, s2, s0
+# CHECK-ASM: encoding: [0x3b,0x33,0x89,0x90]
+pmul.h.b11 t1, s2, s0
+# CHECK-ASM-AND-OBJ: pmul.w.h11 s0, a4, s0
+# CHECK-ASM: encoding: [0x3b,0x34,0x87,0x92]
+pmul.w.h11 s0, a4, s0
+# CHECK-ASM-AND-OBJ: mul.w11 a0, t3, a0
+# CHECK-ASM: encoding: [0x3b,0x35,0xae,0x96]
+mul.w11 a0, t3, a0
+# CHECK-ASM-AND-OBJ: pmacc.w.h11 a4, a4, t1
+# CHECK-ASM: encoding: [0x3b,0x37,0x67,0x9a]
+pmacc.w.h11 a4, a4, t1
+# CHECK-ASM-AND-OBJ: macc.w11 t3, s2, a2
+# CHECK-ASM: encoding: [0x3b,0x3e,0xc9,0x9e]
+macc.w11 t3, s2, a2
+# CHECK-ASM-AND-OBJ: pmulu.h.b00 a4, a2, a0
+# CHECK-ASM: encoding: [0x3b,0x37,0xa6,0xa0]
+pmulu.h.b00 a4, a2, a0
+# CHECK-ASM-AND-OBJ: pmulu.w.h00 a2, t3, t1
+# CHECK-ASM: encoding: [0x3b,0x36,0x6e,0xa2]
+pmulu.w.h00 a2, t3, t1
+# CHECK-ASM-AND-OBJ: mulu.w00 a0, t5, s2
+# CHECK-ASM: encoding: [0x3b,0x35,0x2f,0xa7]
+mulu.w00 a0, t5, s2
+# CHECK-ASM-AND-OBJ: pmaccu.w.h00 t3, t3, t5
+# CHECK-ASM: encoding: [0x3b,0x3e,0xee,0xab]
+pmaccu.w.h00 t3, t3, t5
+# CHECK-ASM-AND-OBJ: maccu.w00 s2, t1, s2
+# CHECK-ASM: encoding: [0x3b,0x39,0x23,0xaf]
+maccu.w00 s2, t1, s2
+# CHECK-ASM-AND-OBJ: pmulu.h.b11 a4, s0, a4
+# CHECK-ASM: encoding: [0x3b,0x37,0xe4,0xb0]
+pmulu.h.b11 a4, s0, a4
+# CHECK-ASM-AND-OBJ: pmulu.w.h11 s0, t5, t5
+# CHECK-ASM: encoding: [0x3b,0x34,0xef,0xb3]
+pmulu.w.h11 s0, t5, t5
+# CHECK-ASM-AND-OBJ: mulu.w11 s0, t1, a4
+# CHECK-ASM: encoding: [0x3b,0x34,0xe3,0xb6]
+mulu.w11 s0, t1, a4
+# CHECK-ASM-AND-OBJ: pmaccu.w.h11 a0, s0, t5
+# CHECK-ASM: encoding: [0x3b,0x35,0xe4,0xbb]
+pmaccu.w.h11 a0, s0, t5
+# CHECK-ASM-AND-OBJ: maccu.w11 s2, t3, t5
+# CHECK-ASM: encoding: [0x3b,0x39,0xee,0xbf]
+maccu.w11 s2, t3, t5
+# CHECK-ASM-AND-OBJ: pmulsu.h.b00 a2, s0, a4
+# CHECK-ASM: encoding: [0x3b,0x36,0xe4,0xe0]
+pmulsu.h.b00 a2, s0, a4
+# CHECK-ASM-AND-OBJ: pmulsu.w.h00 t5, t5, t5
+# CHECK-ASM: encoding: [0x3b,0x3f,0xef,0xe3]
+pmulsu.w.h00 t5, t5, t5
+# CHECK-ASM-AND-OBJ: mulsu.w00 t1, s0, a4
+# CHECK-ASM: encoding: [0x3b,0x33,0xe4,0xe6]
+mulsu.w00 t1, s0, a4
+# CHECK-ASM-AND-OBJ: pmulsu.h.b11 t3, t1, a4
+# CHECK-ASM: encoding: [0x3b,0x3e,0xe3,0xf0]
+pmulsu.h.b11 t3, t1, a4
+# CHECK-ASM-AND-OBJ: pmulsu.w.h11 t1, t3, s2
+# CHECK-ASM: encoding: [0x3b,0x33,0x2e,0xf3]
+pmulsu.w.h11 t1, t3, s2
+# CHECK-ASM-AND-OBJ: mulsu.w11 a2, s2, a2
+# CHECK-ASM: encoding: [0x3b,0x36,0xc9,0xf6]
+mulsu.w11 a2, s2, a2
+# CHECK-ASM-AND-OBJ: pmaccsu.w.h00 a4, a0, t1
+# CHECK-ASM: encoding: [0x3b,0x37,0x65,0xea]
+pmaccsu.w.h00 a4, a0, t1
+# CHECK-ASM-AND-OBJ: maccsu.w00 a4, s2, s0
+# CHECK-ASM: encoding: [0x3b,0x37,0x89,0xee]
+maccsu.w00 a4, s2, s0
+# CHECK-ASM-AND-OBJ: pmaccsu.w.h11 a0, a2, t3
+# CHECK-ASM: encoding: [0x3b,0x35,0xc6,0xfb]
+pmaccsu.w.h11 a0, a2, t3
+# CHECK-ASM-AND-OBJ: maccsu.w11 t5, a4, s2
+# CHECK-ASM: encoding: [0x3b,0x3f,0x27,0xff]
+maccsu.w11 t5, a4, s2
+# CHECK-ASM-AND-OBJ: ppack.h s0, s0, s2
+# CHECK-ASM: encoding: [0x3b,0x44,0x24,0x81]
+ppack.h s0, s0, s2
+# CHECK-ASM-AND-OBJ: ppack.w t5, a2, a4
+# CHECK-ASM: encoding: [0x3b,0x4f,0xe6,0x82]
+ppack.w t5, a2, a4
+# CHECK-ASM-AND-OBJ: ppackbt.h a4, s2, t3
+# CHECK-ASM: encoding: [0x3b,0x47,0xc9,0x91]
+ppackbt.h a4, s2, t3
+# CHECK-ASM-AND-OBJ: ppackbt.w t5, s0, t5
+# CHECK-ASM: encoding: [0x3b,0x4f,0xe4,0x93]
+ppackbt.w t5, s0, t5
+# CHECK-ASM-AND-OBJ: packbt a0, t5, a0
+# CHECK-ASM: encoding: [0x3b,0x45,0xaf,0x96]
+packbt a0, t5, a0
+# CHECK-ASM-AND-OBJ: ppacktb.h t3, s0, t3
+# CHECK-ASM: encoding: [0x3b,0x4e,0xc4,0xa1]
+ppacktb.h t3, s0, t3
+# CHECK-ASM-AND-OBJ: ppacktb.w t5, t1, t1
+# CHECK-ASM: encoding: [0x3b,0x4f,0x63,0xa2]
+ppacktb.w t5, t1, t1
+# CHECK-ASM-AND-OBJ: packtb t5, a4, a4
+# CHECK-ASM: encoding: [0x3b,0x4f,0xe7,0xa6]
+packtb t5, a4, a4
+# CHECK-ASM-AND-OBJ: ppackt.h a0, t1, t5
+# CHECK-ASM: encoding: [0x3b,0x45,0xe3,0xb1]
+ppackt.h a0, t1, t5
+# CHECK-ASM-AND-OBJ: ppackt.w t3, a0, s2
+# CHECK-ASM: encoding: [0x3b,0x4e,0x25,0xb3]
+ppackt.w t3, a0, s2
+# CHECK-ASM-AND-OBJ: packt a2, t3, t1
+# CHECK-ASM: encoding: [0x3b,0x46,0x6e,0xb6]
+packt a2, t3, t1
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