[llvm] [DAGCombine] Fix an incorrect folding of extract_subvector (PR #153709)

[Min-Yih Hsu via llvm-commits]

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@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr='+zve64f,+zvl512b' < %s | FileCheck %s
+
+; Previously, an incorrect (extract_subvector (extract_subvector X, C), 0) DAG combine crashed
+; this snippet.
+
+define <8 x i16> @gsm_encode() {
+; CHECK-LABEL: gsm_encode:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 19, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (zero)
+; CHECK-NEXT:    vslidedown.vi v9, v8, 12
+; CHECK-NEXT:    vmv.x.s a0, v9
+; CHECK-NEXT:    vsetivli zero, 8, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.i v9, -1
+; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v8, v8, 9
+; CHECK-NEXT:    vmv.x.s a1, v8
+; CHECK-NEXT:    vsetivli zero, 8, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vslide1down.vx v9, v9, zero
+; CHECK-NEXT:    vslide1down.vx v8, v8, zero
+; CHECK-NEXT:    vslide1down.vx v8, v8, zero
+; CHECK-NEXT:    vslide1down.vx v8, v8, zero
+; CHECK-NEXT:    vslide1down.vx v8, v8, zero
+; CHECK-NEXT:    vslide1down.vx v8, v8, a1
+; CHECK-NEXT:    vslide1down.vx v8, v8, a0
+; CHECK-NEXT:    vslidedown.vi v8, v8, 1
+; CHECK-NEXT:    vand.vv v8, v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <19 x i16>, ptr null, align 2
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mshockwave wrote:

Fixed retroactively in https://github.com/llvm/llvm-project/commit/0f64ec83f62e4689c886ca3df54ebd49f1169c2c

https://github.com/llvm/llvm-project/pull/153709